SU1480120A1 - Pulse repetition rate divider with controllable pulse duration - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices for producing a series of clock pulses. The purpose of the invention — extending the functionality — is achieved by ensuring the monitoring of the operation of the counters, which makes it possible to control the incorrect operation of the pulse counter when the counter does not fully zero. In this case, the incorrect operation of the pulse counter in the proposed divider does not block the issuance of an alarm signal in case of an error when input codes are supplied. The divider contains a pulse counter 1, code comparison elements 2 and 3, code buses 4 and 5, code comparison element 6, triggers 7.13 and 16, output tires 8 and 9, AND 10 element, OR elements 11 and 12, input bus 14 , bus 15 control, bus 17 unit level. 1 il.

Description

(21) 4318591 / 24-21

(22) 10/16/87

(46) 05/15/89. Bul № 18 (72) Ya.B.Kokhany and V.K.Plish

(53) 621.374.4 (088.8)

(56) USSR Author's Certificate N 1226662, cl. H 03 K 23/66, 10/15/84.

USSR author's certificate number 1403366, cl. H 03 K 23/66, 12.11.86.

(54) THE DIVIDER OF THE FREQUENCY OF THE FOLLOWING OF PULSES WITH ADJUSTABLE LENGTH OF PULSES

(57) The invention relates to a pulsed technique and can be used in automation devices and computer technology to obtain a series of clock pulses. The purpose of the invention — extending the functionality — is achieved by ensuring the monitoring of the operation of the counters, which makes it possible to control the incorrect operation of the pulse counter when the counter does not fully zero. In this case, the incorrect operation of the pulse counter in the proposed divider does not block the issuance of an alarm signal in case of an error when input codes are supplied. The divider contains a pulse counter 1, code comparison elements 2 and 3, code buses 4 and 5, code comparison element 6, triggers 7, 13 and 16, output buses 8 and 9, AND 10 element, OR elements 11 and 12, input bus 14 , bus 15 control, bus 17 unit level. 1 il.

with SS

(L

to

I

00

The invention relates to a pulse technique and can be used in automation and computing devices for producing a series of clock pulses.

The purpose of the invention is to expand the functionality. The goal is achieved by providing the ability to monitor the operation of the counter, which allows controlling the incorrect operation of the pulse counter when the counter does not zero. At the same time, the operation of the counter of pulses (no full reset) in the proposed frequency divider does not block the issuance of an alarm signal in case of incorrect input codes.

The drawing shows an exemplary frequency splitter circuit,

An impulse frequency follower with an adjustable pulse duration contains a pulse counter 1 whose outputs are connected to the first input groups of the first 2 and second 3 code comparison elements, the second input groups of which are connected to the first 4 and second 5 code buses respectively and to the first and second groups of inputs of the third element 6 of the code comparison, the first trigger 7, the inverse and direct outputs of which are connected respectively to the first 8 and second 9 output buses, And 10, the first and second And elements Both 11 and 12, the second trigger 13, the input bus 14 and the control bus 15, which is connected to the direct output of the second trigger 13, the inverse output of which is connected to the first input of the element 10, the output of which is connected to the counting input of the pulse counter 1, the second input - with input bus 14 and clock input of the second trigger 13, the start input of which is connected to the output of the second element OR 12, the first and second inputs of which are connected respectively to the output of More than the third element 6 of the code comparison and the output of the first element OR 11, the inputs of which are connected 1 counter outputs pulses whose reset inputs are connected with the output of the second foam element 3 sraneniyu codes and the reset input of the first flip-flop 7, whose start input is connected to the output of the first element

five

0

Q 5

0

5 0 5 d

2 comparisons of codes, and inverse and direct outputs - with control inputs of the first and second elements 2 and 3 of the comparison codes, respectively, the third trigger 16, the direct output of which is connected to the information input of the second trigger 13, the reset input - with the output of the first element OR 11, the counting input is with the reset input of the pulse counter 1, and the information input is with the unit-level bus 17.

A pulse frequency divider with adjustable pulse duration works as follows.

In the initial state, the pulse counter 1 is reset to a bullet state, the outputs of the first and second elements 2 and 3 of the code comparison are high, the input bus 14 is low, the first, second and third triggers 7, 13 and 16 are reset, the first and second code buses 4 and 5 set codes corresponding to the duration and period of the output pulses, respectively, the code value on the second bus 5 exceeds the code value on the first bus 4, the output of the More than the third code comparison element 6 is high, on bus 15 control - bottom third level.

The clock pulses arriving at the input bus 14 pass through the AND 10 element and trigger the pulse counter 1, which counts them. When the codes at the output of the pulse counter 1 and on the first bus 4 coincide, the first code comparison element 2 generates a low level by which the first trigger 7 is set to one state. The change of states at the output of the first trigger 7 leads to blocking of the first code comparison element 2, the output of which is set to a high level. At the same time, the operation of the second code comparison element 3 is permitted.

At the moment of coincidence of the code value at the output of the pulse counter 1 with the code on the second code bus 5, the second code comparison element 3 is triggered, at the output of which a low level is formed, over which the counter of the first pulses I and the first trigger 7 are reset.

the drop from 1 to O (slice) sets the third trigger 16 to one state. If at the same time all the bits of the pulse counter 1 are set to the zero state, at you during the first element OR 11 a low level is formed, which sets the third trigger 16 to the zero state. After setting the first trigger 7 to the initial state, a low level on the second bus 9 blocks the second comparison element 3, a high level is set at its output, allowing the operation of the pulse counter 1.

Thus, pulses are generated on the first and second output buses 8 and 9, the duration and period of which are determined by the values of the binary codes on the first and second tires 4 and 5, respectively.

When installed on the first code bus 4 code values greater than or equal to the code value on the second bus 5, a low level is formed at the output of More than the third code comparison element 6, which at the moment of pulse counter 0 reset generates a low level at the output of the second element OR 12 sets the second trigger 13 to the one state. At the same time, a high level is generated on the control bus 15, indicating that the input code is incorrect on the first and second code buses 4 and 5, and the low level from the inverse output of the second flip-flop 13 blocks the clock pulses to the counting input of the counter 1 pulses,

If at the moment of zero pulse counter zero setting of at least one bit of the counter to the zero state did not occur, a low level is not formed at the output of the first element OR 11 and the third trigger 16 triggered at the moment of pulse obig the pulse 1 does not reset, therefore the unit level from its direct output will go to the information input of the second trigger 13, after which the next clock slice will set the second trigger 13 into a single state. At the same time, on the control bus 15 a high level will be generated, the signal this time lysing on the incorrect operation of the pulse counter 1, and a low level with inverse

0

five

g 5

0 5 0

five

0

five

The second output of the trigger 13 will block the supply of clock pulses to the counting input of the counter 1 pulses.

Thus, in the proposed frequency divider, the possibility of self-blocking is provided in case of a pulse counter failure (while generating incorrect output information is impossible) with simultaneous output of the alarm output signal.

Claims (1)

Invention Formula Pulse-following frequency divider with adjustable pulse duration, containing a pulse counter, the outputs of which are connected to the first groups of inputs of the first and second code comparison elements, the second groups of outputs of which are connected respectively to the first and second code buses and respectively to the first and second groups of inputs of the third element of the comparison , the first trigger, inverse and direct outputs of which are connected respectively to the first and second output buses, the AND element, the first and second elements OR, the second trigger, input bus and control bus, which is connected to the direct output of the second trigger, the inverse output of which is connected to the first input of the element I, the output of which is connected to the counting input of the pulse counter, the second input to the input bus and the clock input of the second trigger, start input which is connected to the output of the second element OR, the first and second inputs of which are connected respectively to the output of More than the third element of the comparison codes and the output of the first element OR whose inputs are connected to the outputs of the counter pulse in, the reset input of which is connected to the output of the second code comparison element and the reset input of the first trigger, the start input of which is connected to the output of the first code comparison element, and the inverse and direct outputs to the control inputs of the first and second code comparison elements, respectively, that, in order to expand the functionality by ensuring the control of the counter, a third trigger has been introduced in it, the direct output of which is connected to the information input of the computer 51480120. 6 trigger trigger, the reset input is connected to a pulse counter, and the information input is connected to the output of the first OR element, the counting input is connected to the bus, a single input is connected to the level reset input.