SU1106012A1 - Code-to-cumulative time interval converter - Google Patents

Abstract

1. CODE CONVERTER TO TOTAL TIME INTERVAL, containing a pulse generator and a controlled frequency divider, the setup inputs of which are respectively connected to p input buses, characterized in that, in order to increase the conversion accuracy, the first and second triggers and a logic inverter are introduced into it, the input of which is connected to the output of the pulse generator and the synchronization input of the first trigger, and the output to the counting input of the second trigger, the output of which is connected. to the counting input of a controlled frequency divider, the output of which is connected to the information input of the first trigger, the output of which is connected (L to the output bus.

Description

2. The converter according to claim 1, characterized in that the controlled frequency divider is made on a n-bit bottom binary pulse counter, an OR element and an AND element, the outputs of which are connected to the corresponding inputs of the OR element, the output of which is connected to the output of the controlled frequency band, the installation inputs of which are connected: Hb1 with the first inputs of the corresponding tickle elements AND, the second inputs

which are combined and connected to the counting input of the controlled frequency divider and the input of the n-bit binary pulse counter, the inverse outputs of the bits of which are connected to the third inputs of the corresponding AND elements, and the remaining i-1 inputs of each g, -th element AND, except of the first one, respectively, are connected to the direct outputs of all previous bits of the binary pulse counter.

The invention relates to a pulse technique, in particular, to a code converter in a time interval, and can be used to build precision code to voltage converters with an intermediate conversion into a number of pulses of stable duration. A known converter of code into a time interval containing a counter, a pulse generator, a trigger and a logic element I, in which the first inputs of the counter are connected to the code inputs of the device, the inputs of the logic element I are connected to the outputs of the pulse generator and the trigger zero setting input connected to the overflow output of the counter SP The disadvantage of this device when used in a code to voltage converter with intermediate conversion into a cumulative time interval is that the output mpulsy Delena uneven distribution of the repetition period. This leads to an increase in the ripple at the output of the low-pass filter, which is usually used in code-to-voltage converters with an intermediate conversion to a number of non-touching pulses, the duration of which during the conversion period form the total interval in meni. The closest to the proposed technical entity is a code to total time converter, containing a pulse generator and a frequency divider control, the setup inputs of which are connected to the P input buses, the counting input connected to the output of the pulse generator, and the output to the output bus C2. In this converter, the number of output non-touching pulses during the conversion period is distributed more evenly, which reduces the ripple in the output signal of the code-to-voltage converter based on the intermediate converter. However, this converter is also characterized by a disadvantage, which is expressed in the violation of identity in terms of the duration of the output pulses, since with different codes the output pulse is formed by different logic elements with nonidentical delays. The purpose of the invention is to improve the accuracy of the conversion. The goal is achieved by the fact that the first and second triggers and a logical inverter, whose input is connected to the output of the pulse generator and the synchronization input of the first trigger, and the output with the counting input of the second trigger, the output of which is connected to the counting input of the controlled frequency divider, the output of which is connected to the information th input of the first trigger, the output of which is connected to the output power supply.

In this case, the controlled frequency divider is made on a n-bit bottom binary pulse counter, the OR element and g AND elements, the outputs of which are connected to the corresponding inputs of the OR element, the output of which is connected to the output of the controlled frequency divider, the setup inputs of which are connected to the first inputs the corresponding elements And, the second inputs of which are combined and connected to the counting input of the controlled divider - frequency and the input of the 1L -discharge binary pulse counter, the inverse outputs of the bits of which are connected to the The other inputs of the corresponding elements I, and the remaining parts of the –1 inputs of each rth element AND, except the first, are respectively connected to the direct outputs of all the previous bits of the binary pulse counter.

Figure 1 shows a structural electrical converter circuit; Fig. 2 is a schematic of an embodiment of a controlled frequency divider.

The converter contains input rails 1, control divider 2 frequencies with variable division factor with second input 3 and output 4, generator 5 pulses, logic inverter 6, triggers 7 and 8, output bus 9, P-bit binary counter 10, inverse 11 and direct 12 outputs of the first (low) bit of this counter, inverse 13 and direct 14 outputs of the second discharge of the counter, inverse 15 and direct 16 outputs of the n-1 bit counter, inverse output 17i | th (senior) bit of the counter, first 18, second 19 and n th 20 logical gates And, logical element 21 OR.

In the converter, the input buses 1 are connected to the corresponding installation inputs of the divider 2, the output of the generator 5 is connected to the synchronous input of the first trigger 8 and through the inverter 6 to the counting input of the second trigger 7, the output of which is connected to the second input 3 of the divider 2, the output 4 of which is connected to the information } the input of the trigger 8, the output of which was the rtsyp. total converter and connected to the output bus 9.

In the controlled frequency divider 2, the first inputs are the first inputs of logic elements 18-20, and the input of the older bit of the code being converted is the input of element 1 and the low-order input is the input of element 20. The second input 3 of divider 2 is connected to the counting input counter 10 and with the second inputs of elements 18-20, the third inputs of which are connected to the corresponding inverse outputs 11, 13, 15 and 17 of the counter 10. The remaining inputs of elements 19 and 20 are connected to all the direct outputs of the preceding least significant bits of counter 10 (for 19 with you Odom 12 for element 20 - to the outputs 12,14-16). The outputs of the elements 18-20 through the element 21 is connected to the output of the divider 2.

The device works as follows.

Signals arriving in parallel to the input buses 1 are converted in divider 2 into a proportional number of non-overlapping pulses at its output, which arrive at the information input of the trigger 8. The frequency of these signals is determined by the value of the code being converted and the frequency of the output pulses of the trigger 7, which is two times lower the frequency of the output pulses of the generator 5. At the same time, the trigger of the trigger 8 occurs on the front of the output pulse of the generator 5, and the trigger of the trigger 7 - on the decline of this pulse, the output pulses of the trigger 8 and the splitter 2 are shifted relative to each other by the magnitude of the pulse duration of the generator 5. The output of the trigger 8 produces pulses similar to the pulses at its information input, but shifted relative to them by the magnitude of the pulse of the generator 5. Moreover, the duration of the output pulses of the proposed converter is independent on the value of the code being converted, as determined by the period following the output pulses of the generator 5 and the delays introduced by the same element - trigger 8. th frequency divider 2 produces on

Exit 4 non-overlapping pulses. If there is a unit in the higher order de transform-1 code, then 51 is open on the first input element 18, and signals passing to the input 3 of the frequency divider pass through it, in those moments when the low-order counter is in the zero state i.e. at the output of element 18 pulses of the highest frequency are formed. At the output of element 19, pulses are similarly formed, but if there is a unit in the next most senior bit of the code being converted, but at the moment when the low discharge of counter 10 is in the unit state, and its second lower bit is in the zero state nii, i.e. at the output of element 19, pulses are formed with a frequency of two times less than at the output of element 18, etc. At the output of the element 20, controlled by the inverse spin 13 (the high bit of the counter 10, if there is one in the lower bit of the code to be converted, during the period of operation of this counter, only one pulse is generated at the time of coincidence of the unit states in all the lower bits of the counter 10 Thus, the converter allows to obtain precision output pulse signals that are strictly identical in duration, the number of which is equal to the value of the code being converted. The technical effect of the use of the invention lies in the fact that the output sequence pulses in the proposed device have a much greater identity and stability in duration, which significantly improves the accuracy of code conversion to the total time interval. The improvement in identity and stability is confirmed as follows. The pulse duration at the output of a logic element is generally determined by the expression U tu4-t-j $ -fcic. where is the duration of the input impulse, the front delay time, the decay delay time. Usually, tjj, so you can write, ty iaxt At, where t r-tsq, - t) For the proposed scheme, we have tn fcgy t-q-b-3 (you can take any sign, but any one for a particular type trigger 8). For the prototype, the output pulse is ty. -t.du ± d-tj, and for different values. g delay Lai may be different both in sign and in magnitude due to the nonidentity of the parameters of various logical elements. Thus, the duration of the output pulses of the converter is strictly constant regardless of the value of the code being converted.

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Claims (1)

1. CODE CONVERTER In the TOTAL TIME INTERVAL, containing a pulse generator and a controlled frequency divider, the installation inputs of which are respectively connected to η input buses, characterized in that, in order to increase the conversion accuracy, the first and second triggers and a logical inverter are introduced into it, the input of which is connected with the output of the pulse generator and the synchronization input of the first trigger, and the output with the counting input of the second trigger, the output of which is connected. to the counting input of a controlled frequency divider, the output of which is connected to the information input of the first trigger, the output of which is connected to the output bus. SU, ·· 1106012 1106012 unitary enterprise. The converter according to claim 1, characterized in that the split frequency divider is made on an η-digit binary pulse counter, an OR element, and n AND elements, the outputs of which are connected to the corresponding inputs of the OR element, the output of which is connected to the output of a controlled frequency divider, the installation inputs of which connected to the first inputs of the corresponding AND elements, the second inputs of which are combined and connected to the counting input of the controlled frequency divider and the input of the and-digit binary pulse counter, inverse outputs of the discharge s are connected to respective third inputs of AND gates, the remaining t-1 inputs of each AND £ th element except the first are respectively connected with the direct outputs of all the preceding bits of the binary pulse counter.