SU544112A2 - Device for multiplying the frequency of the following pulses - Google Patents

Description

The invention relates to automation and measurement technology and can be used in digital meters of $ 1x frequency. A device is known for multiplying the periodic pulse frequency, which contains a reference frequency divider, with a division factor equal to the multiplication factor, a reference frequency pulse counter, a pulse counter, a driver, which stores a register, two blocks of time: a, built on schemes I, and a control unit However, this device is characterized by the discreteness of the error due to the non-multiplicity of the number N of the pulses of the generator of the reference frequency foni received during the period T of the multiplied frequency f to the input of the divider, the ratio to the division. As a result, the number of the fractional part of the N / K division may remain to the horse of each period T. in the divisor, which is reflected in the error of the pulse sequence of the output sequence reaching in the limit of magnitude. The purpose of the invention is to increase the multiplication rate. To this end, the multiplier, containing the reference frequency divider with a division factor equal to the multiplication factor, a reference frequency pulse counter, drivers, a storage register, two transfer units and a control unit, has an additional transfer unit, an additional storage register, a decoder, and matching elements. , draw lines & ki, an OR element and a logic device consisting of a trigger and AND elements, the first inputs of which are connected to the reference frequency source, the second inputs - to the trigger outputs, the first input of which is connected to the output of the input shaper, and the second input is connected to one of the outputs of the control unit, the other outputs of which are connected to the inputs of the additional transfer unit and the additional storage register, the output of one of the And elements connected to the input of the control unit, and the output of the second to the input of the reference frequency divider, whose single outputs through an additional transfer unit and an additional storage register, which are connected in series, are connected to the inputs of the decoder, while Exit deshi4 Rhatore with di enes with perzymi inputs deii elements coincide, the second inputs of which are combined and connected to the output of the output driver, the first output directly, and outputs the remaining through delay line are connected to inputs of the OR element. The drawing shows the structural electrical circuit of the device for a very short periodic pulse frequency. The device contains a divider 1 reference frequency with a division factor K, counted 2 pulses formed when dividing the reference frequency, input driver 3, counter 4 pulses of reference frequency, register register 5, output driver 6, control block 7, blocks 8 and 9 of transfer codes , built on AND gates, additional block 10 transfer code, additional storage register 11, decoder 12 match elements 13, delay line 14, element OR 15, logic element 16, consisting of trigger 17 and elements 18 and 19. Device The event works as follows. Each gpulse of the frequency to be multiplied f. through the input driver 3 enters the zero input of the trigger 17, which, throwing over, opens element 19 for convincing reference frequency pulses to the input of block 7. During the time that the block 7 receives pulses of frequency f, this block produces three signal, the first of which sets in, O all bits of diminishing registers 5 and 11, the second nocJTnaer and the second inputs of the circuits AND blocks S to 10 k transfers the return code from counter 2 to the storage register 5 and the forward code from the divider 1 in memory register 11, the third sets all bits to 2 in state 1 and writes in the divider 1 a number equal to the number of pulses HaCTOtbt fon I passed to the input of block 7. At the same time, the third signal from block 7 flips the trigger 17 and opens element I18 to pass pulses fofjua the input of the divider 1, Pulses from the output divider 1, the frequency of which hash is equal to fop / K, is fed to the input of counter 2. For one period Td, the pulses of the multiplied frequency f followed to the input of counter 2, the number of pulses is equal to Nc N K-TOH With this, in divider 1 by the end of the period ( pin number ni, due flax Noe nonmultiple number N of pulses supports hydrochloric frequency received at the input of the divider, the coefficient K ((n i K) Since all the bits of the counter 2 rows have been previously installed in, the counter 2 is fixed number equal to Ny - J. This number is eaten by the arrival of the next pulse of the multiplied frequency by the signal from block 7 is transferred in the reverse code by block 8 to the memory register 5 and, thus, the additional code of the number N is set in register 5. At the same time, with the same signal from block 7, the remainder m from divider 1 is transferred to the memorized register 11. At the same time, the reference frequency pulses are continuously fed to the input of counter 4. Each overflow pulse from the output of counter 4, the output driver 6, is fed to the second yasody elements of AND block 9, through which The transfer of an additional code of the number NX from the storage register 5 to the counter 4. As a result, at the output of the output shaper 6, a sequence of pulses is formed with a following period. Tsw T s-Ei AT on 1 However, in reality, the period T is less than determined by the residual number. tn in divider 1. In the limit, this reduction is the value and, thus, taking into account the maximum discreteness error, the expression for the follow-up period at the output of the output driver 6 will write T -Ik- T 1 K op To reduce the error of the discreteness of the output generator signal 6 is fed to one of the inputs of the matching elements 13, the other inputs are connected to the corresponding outputs of the decoder 12. The decoder 12 analyzes the state of the storage register 11 and, depending on the number fTi, gives the resolving potential The first input is the corresponding matching element 13. The number of output buses of the decoder 12 is determined by how much (N times) it is required to reduce the discretization error. In this case, if the number t - jTO the resolving potential appears at the first input of that element of coincidence 13, the output of which is directly connected to the input of the element OR 15, At - 4 the resolving potential appears on the decoder bus 12 connected to the first input coincidence element 13, the output of which is connected to the input of the element OR 15 through the line of the backwater 1 with the time to the top of G - IP, with 2-4 n connection to the input of the element OR 15 pro ILO O

; the descent of G through lithium delay 1-9 with L- 1 pu through the delay line 14 with 5 Ta, etc.

Thus, if the signal from the output of the imaging unit 6 is applied to the second inputs of the elements of the co-ownership 13, then the period of its repetition on the code of the element OR 15 will be taking into account the maximum PS of the discreteness error determined; excretion

T -Ik- °

BWXK n

15

fu the maximum discreteness error is reduced by n times. This increases the stability of the multiplication factor, decreases the phase-pulse modulation of the output signal, and extends the working frequency range. Indeed, the condition for the absence of coefficient jumps; multiply K is written as:

25

K 1x -1

Pe

; from where

thirty

f IL

The latter are interpreted hardly in the following way:

1. The range of the frequency to be multiplied is increased by a factor of 1.

2. When fx is saved, it is possible in n, .az to reduce fg, j (decrease the speed of the counters) or increase it accordingly, 1

multiply multiplier.

Vyralhenne dl as possible. ; yu phase instability of the output pulses of the multiplier will be written in the form (in radians)

utp-aft-t. e., the Fae-pulse modulation of the output signal 1 is reduced T1 times.

Claims (1)

Invention Formula A device for multiplying the frequency following a periodic pulse, according to the author. St. N 357668, characterized in that, in order to increase the multiplication accuracy, an additional transfer unit, an additional storage register, a decoder, coincidence elements, delay lines, an OR element and a logic device consisting of a trigger and AND elements, whose first inputs are entered into it. connected to the source of the reference frequency, the second inputs to the trigger outputs, the first input of which is connected to the output of the input driver, and the second input to one of the | Outputs of the control unit, the other outputs of which are connected to the inputs of the additional Transfer unit and the additional storage register, the output of one of the elements, and is connected to the input of the control unit, Ava; second stroke - to the input of the reference frequency divider, which unit outputs through complement Tel'nykh transfer unit and the additional zapomi. the serial register, which are connected in series, are connected to the inputs of the decoder; the outputs of the decoder are connected to the | first inputs of the coincidence elements, the second inputs of which are combined and connected: You to the output of the output driver, you; delay lines are connected to the inputs of the element OR.