SU766032A1 - Discrete signal transmitting and receiving device - Google Patents

Description

one

The invention relates to radio engineering and can be used in asynchronous address communication systems for transmitting messages.

A device for transmitting and receiving discrete signals is known, comprising, on the transmitting side, an address encoder, the input to which is connected to the first input of the first element AND and the input of the counter, the first output of which is connected to the second input of the first element And whose output through the encoder; information is connected to the input of the element N MLHD of which is connected to the first input of the second element AND, the output of which is connected to the first input of the modulator, to the second input of which the output of the OR element is connected, the first input of which is connected to the output of the address encoder, and on the receiving side - the decision unit and follow- directly connected threshold block and address decoder, the output of which is connected to the first input of the element I, the output of which is weak with the first input

counter, the output of which is connected to the first input of the decoder and 1C |) Ormation, while the second input of the element And the clock signal l.

However, the noise immunity of the known device is low.

The purpose of the invention is to improve the noise immunity of the device.

For this purpose, in the proposed device for transmitting and receiving discrete signals on the transmitting side, the third And element and the trigger, whose input is connected to the first output of the counter, the second output of which is under-, the keys to the first input of the third And element, the second input and which is connected respectively to the output of the coder formay and the second input of the OR element, and the trigger output is connected to the second input of the second element AND and the third input of the first AND, on the receiving side a control unit is inserted, the inputs of which are connected to the inputs and the output of the decision block.

the first output of the control unit is connected to the input of the threshold unit, the code of which is connected to the additional control unit code, the second and third output, which is connected respectively to the second inputs of the counter and information decoder, and the corresponding input of the control unit is connected to the output of the address decoder.

The drawing shows a structural electrical circuit of the proposed device.

The device contains on the transmitting side 1, the address coder 2, the counter 3, the first element AND 4, the information encoder 5, the element NOT 6, the second element And 7, the modulator 8, the element OR .9 and the third element And 10, and on the receiving side 14 - a decisive block 12, a threshold block 13, an address decoder 14, an AND 15 counter 16, an information decoder 17 and re-entered on the transmitting side

I- trigger 18, and on the receiving side

II-control unit 19.

The device works as follows.

On the transmitting side 1, the input pulses are fed to the input of the address coder 2, to the input of counter 3 and to the first And 4 element. In the original

The first state 4, second 7 and third 10 elements And signals do not pass. The address 2 encoder contains a Charman sequence containing M symbols 1 among N positions, where M M. Each symbol I from the Yotkhoda address encoder 2 through the element OR 9. Enters the input of the modulator 8 and further to the output in the form of frequency i. During the first n cycles the code is generated.

addresses in the form of parcels, frequency 1 | and pauses / between them. After this, the address 2 encoder stops working.

After passing the clock pulses, the signal from counter 3 arrives at trigger 18, which resolves the location of signals through the first 4 and second 7 elements I. The next clock impulse passes through the first element 4 and to the input of the information coder 5, where the first N characters of information are written in reverse code, that is, on the ground recorded O, and vice versa. If the symbol I appears at the output of information encoder 5, then there is no signal at the output of element 6, therefore there is no signal and the input of the second element 7 and module 8 forms a pause. If the exit

information encoder 5. the symbol O arrives, then at the output of the NOT 6 elivta there is a signal that passes through the second element And 7 passes to the second input of the modulator 8, and the latter forms the frequency sending in.

After a cycle has passed (only 2 N cycles from the beginning of operation) the signal from the output of counter 3 is fed to the input of the third element And 10, the counter .3 stops working. Now the characters 1 from the output of the information encoder 5 through the third element AND 10 and the element OR 9 are passed, to the first input of the modulator 8 and emitted by the frequency, and the symbols O through the element NOT 6 and the second element And 7 to the second input of the modulator B and are emitted in frequency.

Claims (1)

Invention Formula A device for transmitting and receiving discrete signals, comprising, on the transmitting side, an address coder, the input of which is connected to the first input of the first element AND and the input of the counter, the first output of which is connected to the second input of the first element And, output. which through the information encoder is connected to the input element NOT, the output of which is connected to the first input of the second element AND, the output of which is connected to the first input of the modulator, to the second input of which the output of the element OR is connected, the first input of which is connected to the output of the address encoder, and at the receiving to the side - a decisive block and a serially connected threshold block and an address decoder, the output of which is connected (and the first input of the element I, the output of which is connected to the first input of the counter, the output of which is connected to the first input of the decoder The information generator, at the same time, the second input element And the clock signal, characterized by 4TOi in order to improve noise immunity, is supplied on the transmitting side, the third element I and the trigger, the input of which is connected to the first output of the counter, the second output of which is connected to the first input of the third element And, the second input and output of which are connected respectively to the output of the information encoder and the second input of the OR element, and the output of the third input is connected to the second input of the second element AND and the third input of the first element AND, on the receiving side A control unit E is entered, the inputs of which are connected to the inputs and output of the decision unit, the first control output connected to the input of the threshold unit whose output is connected to the auxiliary input of the control unit, the second and third outputs of which are connected respectively to the second inputs, and information decoder, and the corresponding input of the control unit is connected to the output of the address decoder. Sources of information taken into account in the examination. 1. Technical report on the research work of Barrier-2, register No. 702070, L., 1974 (prototype).