SU1370725A1 - Matched digital filter of composite signals - Google Patents

Abstract

Invention m. Used in large-base pseudo-random signal processing devices. The purpose of the invention is to improve noise immunity. The filter contains an input quantizer, links of matched filters, Mr. pulsed sequences and Mr. clock pulses. The matched filter contains registers 5, 9, 11, and 12, memory block 6, address counter 7, switch 8, algebraic. adder 10 and rr 13 reference sequences. All links of the matched filter work on one algorithm in parallel. At the output of the last link, samples of the mutual correlation function of the received and reference signals are formed for the input sample streams of equal parity. 3 il. with f

Description

(L

The invention relates to a technique for transmitting discrete signals and can be applied in devices for processing pseudorandom signals with a large base.

The purpose of the invention is to increase the noise immunity of the digital matched filter of the composite signals.

FIG. 1 shows a block diagram of a digital matched filter of composite signals; figure 2 - structural diagram of the link matched filter; in fig. 3 is a timing diagram explaining the structure of the input pseudo-random signals; in fig. A is a timing diagram explaining the work of the matched filter link.

The digital matched composite signal filter contains an input quantizer 1, links of 2 matched filters, a generator of 3 pulse sequences and a generator of 4 clock pulses.

The link 2 of the matched filter contains the first register 5, the RAM block 6, the address counter 7, the switch 8, the second register 9, the algebraic adder 10, the third 11 and the fourth 12 registers and the generator 13 of the reference sequences.

Digital matched filter composite signal works as follows.

The transmitted and reference composite signals (e.g., second order) are generated in accordance with the diagram in FIG. 3. The elements of the periodically repeating first pseudo-random sequence (PSP1) a are multiplied with the elements of the second pseudo-random sequence (PSP2), where a.,, 2, k r7T; 7; N and N, p are the numbers of the elements PSP1 and PSP2, respectively, and the duration of the elements PSP2 is equal to the duration of PSP1. The base of the composite second order signal is -Nj. Composite signals of the third and higher orders are constructed similarly. The values of the elements a of the reference sequences,, Nj,, 1 are formed by the generators 13 of the reference sequences under the action of the clock pulses of the generator 3 of the pulse sequences and in the form of logic levels are fed to the control

ten

707252

Leading inputs of 10 link algebraic adders 2.

The mixture of the received video signal and interference is fed to the input of the input quantizer 1, at the output of which samples X are formed. To ease the clock synchronization requirements, it is necessary for the input quantizer 1 to form two samples per element of the composite signal. In this case, the stream of samples at the input of the first link 2 can be divided into two streams with even and odd values of the K number (two streams of samples of equal parity). In each of these, one sample of the input quantizer 1 is counted per signal element.

In the first link 2, in the time interval between two samples of the input quantizer 1, the quantity

If

20

h,

 v

H. A

Have

P :

(I)

where the samples of the input quantizer I are renumbered so that X is the last received sample regardless of its parity. Thus, Xj is the cross-correlation function (PVC) of the segment of the received composite signal and the SRP1. The X values are transmitted to the second link 2, in which the value of

(2)

where the counts FVK X at the input of the second link 2 are renumbered so that the last arrived count has a number. In view of (l) and (2)

x .I

 L. J

Ni

I and X

N

 Lb

(Y

g

0

five

Where

- the value of the elements of the second-order composite composite signal;

m (k-l) N, + i,, N,, ,, ,, x; There is a PVC of the received cd signal

those,

(flow of samples equal parity,

with the reference composite signal of the second

for now.

In the 1st link 2, operations are performed in accordance with the algorithm

k.-

where the samples X are renumbered so that the last incoming to the i-e link 2 the count has a number.

Thus, all links 2 work according to the same algorithm (G) and at the output of the last 1 link 2, FVC samples of the received and reference signals are formed for the streams of input samples of equal parity, i.e. two PVC values per element of the composite signal. All links 2 function in parallel and each of them performs Nf operations of summing input samples at the base of the composite signal M ... N

I ... 11.

In accordance with the algorithm (3) link 2 works as follows.

The generator 3 of the pulse sequences from the signals of the generator A generates a series of control pulses (an example of timing diagrams is shown in Fig. 4). The generator 3 is started by a start signal from the input quantizer 1. By the signal W the input count X is recorded in the first register 5 and through it is fed to the first input of the switch 8, which at the beginning of the processing cycle connects the output of the register 5 to the input of the block 6. By the signal W ; The incoming input count is recorded in block 6, and switch 8 switches to data transfer from block 6 to input of the second register 9. With the same signal, the third register 11 is reset to zero. Then, by the first signal T, the contents of counter 7 are increased by 2 in the first link

2 and N N

N

3 i-M link 2 (172), thus ensuring, by the sag-th, renumbering the input stream of samples of equal parity in accordance with (3). Counter 7 provides an arithmetic calculation modulo M, 211 in the first link 2 and N; N, N5. .. K, - in the remaining links x 2 (). The capacity of unit 6 must be at least M; memory cells. At the end of the first signal T. from block 6, the value X is read, which through switch 8 is fed to the input of the second register 9 and written into it by the first pulse R. From the output of the second register 9, the samples are fed to the first input of the algebraic adder 10, and to the second his entrance to

5 o

x

this time, the zero content of the third register 11 is fed. The input to controlling the operation mode of the algebraic adder 10 is given a pseudo-random sequence element from the generator 13, and the output of the adder 10 forms the value of the product a X, which is the first pulse P, entered into the third register 11. In this time of the second pulse T, soder; Counter count 7 is increased again by 2 in the first

N.

in the 1st star 2 and on N, K,, not 2 (), and the procedure is repeated. After the Nth pulse P, the third register 11 contains the value X in accordance with (31, and the counter 7, the pulse t, is incremented by 1, preparing block 6 to write the input reference in the next processing cycle. With the pulse W, the value from the third register 11 is entered into the fourth register 12 for transmission to the next link 2, and the switch 8 switches to transmitting data from the first register 5 to the block 6. The link 2 returns to the initial state.

Claims (1)

Invention Formula A digital matched filter of composite signals containing a series-connected input quantizer whose input is an input of a digital matched filter of composite signals and 1 link of matched filters, where 12, the output of the last of which is the output of a digital matched filter composite signals, serially connected clock generator and pulse sequence generator, the outputs of which are connected to the corresponding control inputs of matched filter links, characterized in that, in order to increase noise immunity, the output signal of the input quantizer trigger signal is connected to the trigger input of the pulse sequence generator, and each link of the matched filter contains sequentially connected first register, whose input is a matched filter link input, a switch, a second register, an algebraic adder, a third register, and a fourth register, the output of which is the output of a matched link 513707 filter, the address counter, the output of which is connected to the address input of the RAM, the input and output of which is connected to the second output and input of the switch, respectively, and the generator of the reference sequences, the output of which is connected to the control input of the algebraic adder, the second input which is connected to the output of the third register, 10 moreover, the input of the first register, the input of the recording of the RAM block, combined with the first control 56 switch input and the third register reset input, the read input of the RAM block, combined with the second register record input and the reference sequence generator, the first and second clock inputs of the address counter, the second control input of the switch, combined with the fourth register record input, and the third register entry input is the corresponding control inputs of the matched filter link. B} (one phage. Composite signal The second pair d / a Fig.Z Output cpus