SU1167527A1 - Digital meter of phase shift - Google Patents

Abstract

DIGITAL MEASURING SHEAR PHAZ containing a series-connected formation unit, a coincidence unit and a pulse counter, a pulse generator, a reversible counter, a control unit, an adder, the output of the pulse generator connected to the Coincidence unit, the inputs of a reversible counter, ConnectionG; the outputs of the formation unit and the control unit, the input of the control unit is connected to the output of the formation unit, and the outputs are connected to the control inputs of the pulse counter and the adder, characterized in that it is fast for the purpose of innovation. action, it introduced two multiplexers and k registers; memory, the output of the pulse counter is connected to one input of the first multiplexer, the outputs of the multiplexers are connected to the inputs of the adder, the output of which is connected to the inputs of memory registers, the outputs of which are connected to the corresponding inputs of the first and second multiplexes (L sor, the output of the k-th register memory This is the output of the device, the output of the reversible counter is connected to the control unit, the outputs of which are connected to the control inputs of the multiplexers and memory registers.

Description

The invention relates to a radio measuring technique and can be used to measure phase shift with noise immunity. The purpose of the invention is to increase speed. FIG. 1 shows a block diagram of the device; in fig. 2 - control signals for the operation of the adder. The device contains a forming unit 1 consisting of drivers 2, 3 and logic unit 4, a unit 5 connected in series, a coincidence unit 5, a pulse counter 6, a first multiplexer 7, an adder 8, a second multiplexer 9, registers. 10J -, a pulse generator 11, a reversible counter 12 and a control unit 13, the inputs of logic unit 4 connected to the outputs of drivers 2 and 3, and the output - to a coincidence unit 5 connected to a generator 11 of pulses, the output of adder 8 connected to inputs registers 10–10 memory, the outputs of which are connected to the corresponding inputs of multiplexers 7 and 9, the output of multiplexer 9 is connected to the second input of the adder 8, the inputs of the reversing counter 12 are connected to the outputs of the forming unit and the control unit 13, and the output to the control unit 13 control unit 13 Connected with an input: with a formation unit 1, and outputs with a counter of 6 pulses, a multiplexer 7, 9 with an adder 8 and registers 10, - 10k memories. The device works as follows. The measured and reference signals are fed to the inputs of drivers 2 and 3, respectively. Direct limited bursts from the outputs of the formers 2 and 3 are fed to logic block 4, the output of which removes a sequence of pulses, the logical units of which correspond to intervals (i (n) of mismatch of the polarities of the input -.t, pulses of duration 360 where q is the phase the shift of the input signals, which fluctuates under the influence of interference, T is the period of the signals. Block 5 coincides with pulses from the output of logic block 4 and passes counting pulses with a frequency of 272 pulses from the generator 11 to the counter input. The pulses received at counter 6 for the first signal period, equal to h, 2iq. The code of the number P from counter 6 is fed through multiplexer 7 to adder 8. Adder 8 performs summation over k cycles generated by the control unit.13, and in the first cycle The adder 8 performs the addition of the code of the number P (from counter 6 and the code of the number from the register 10 of the memory received through the multiplexer 9. The result of the addition is recorded in the register 1-0, / memory. In the second cycle, codes of numbers coming through multiplexers 7 and 9, respectively, from registers and memory W2 are added, and the result of the addition is recorded in memory register IOg, etc. In the last kth summation cycle, depending on the control signal from (-t) coming from control unit 13, register register 10 is added to register code 10 (; memory received through multiplexer 9). memory, and the result is entered into register 10 to the memory, or register code 10k "1 memory is subtracted from the register 10 code to the memory. At the end of the second period of the signal in counter 6, the code of the number O, + + I1j (n2 7a5 o which is fed through multiplexer 7 is fed to the adder 8, performing the summation of the codes in the k cycles described above. The total number of pulses accumulated in register 10 the memory during the measurement time Tj, J equal to m periods of the input signal (Ti, m) is determined by the formula and is uniquely related to the average value of the measured phase shift: where r) j is the number of pulses in. . ; counter 6 for the signal period; a weighting factor, the value of which is determined by the type of the implemented weight function generated by the control unit 13. Obtaining a given weighting function is performed by generating control signals oc (t), examples of which are given in. FIG. 2

3

In the simplest case, for a triangular weight function, it is necessary to generate a control signal shown in FIG. 2a, the number of memory registers is in this case equal to k 1. Thus, up to half of the measurement time T of the register codes; 10 memory codes are accumulated in counter 6, and the result is written to register 10 (; memory, during the second half of the measurement time, memory register codes 10c are added to counter codes 6. For a triangular weighting function, formed in this way, takes on the value of:

174 mt-1 g T1 I l - -5-- -2 41

-J An increase in the noise immunity of the proposed phase shift meter with respect to the spectrum-concentrated noise is achieved by using more complex control signals (for example, FIG. 2b) while simultaneously increasing the number of memory registers 10 ((k 3). To generate control signals for OS ( i) a reversible counter 12 records the number of periods or- groups of periods of the input signal (n during the measurement time T, 5) beats

675274.

by counting the pulses from the driver 2 of the reference signal. For example, for a triangular weight function, the reversible counter 12 is half the measurement time, works for addition, and from half the measurement time for subtraction, which ensures the symmetric formation of the control function

10 ", (1) (Fig. 2a). The control unit 13 resets the counter 6, controls the operation of the multiplexers 7 and 9, |) of the register 10 - 10 memory, the reversible counter 12, and also

f5 control of the summation mode of the adder 8.

Thus, in the proposed phase shift meter, the weight processing of information is carried out

0 by multiple summing (mpoj) of the measured information in k cycles. The summation of information takes 5-10 times less time than the multiplication operation,

5, the weight measurement process in the prototype takes place in (5-10). m times more time than in the proposed device. The proposed measurement of the shift phase has great speed

Q compared to the prototype, more accurate and easier to manufacture.

Claims (1)

A DIGITAL PHASE SHIFT METER containing consecutively connected forming unit, coincidence unit and pulse counter, pulse generator, reversible counter, control unit, adder, wherein the output of the pulse generator is connected to matching unit, inputs of the reversible counter are connected to the outputs of the forming unit and control unit, input control unit connected to the output formation unit, and outputs - a pulse counter and the control inputs _(the adder, characterized 'in that, in order to enhance fast-action, no. o two multiplexers were introduced to the registers: memory, the output of the pulse counter connected to one input of the first multiplexer, the outputs of the multiplexers connected to the inputs of the adder, the output of which is connected to the inputs of the memory registers, the outputs of which are connected to the corresponding inputs of the first and second multiplexers, the output to - memory register is the output of the device, the output of the reversible counter is connected to the control unit, the outputs of which are connected to the control inputs of the multiplexers and memory registers. 1167527 2