US5774003A - Flip-flop cell having clock skew protection - Google Patents

Flip-flop cell having clock skew protection Download PDF

Info

Publication number
US5774003A
US5774003A US08727289 US72728996A US5774003A US 5774003 A US5774003 A US 5774003A US 08727289 US08727289 US 08727289 US 72728996 A US72728996 A US 72728996A US 5774003 A US5774003 A US 5774003A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
flip
flop
input
clock
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08727289
Inventor
Fazal Ur Rahman Qureshi
Martin William Person
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Abstract

A flip-flop cell having a main data input, a main scan data input, a main data output and a main clock input. The flip-flop cell includes a multiplexer having first and second inputs and an output. The first input is coupled to the main data input of the flip-flop cell and the second input is coupled to the main scan data input of the flip-flop cell. A first latch has a data input, a data output and an inverting clock input. The data input of the first latch is coupled to the output of the multiplexer. A second latch has a data input, a data output and a non-inverting clock input. The data input of the second latch is coupled to the data output of the first latch. A third latch has a data input, a data output and an inverting clock input. The data input of the third latch is coupled to the data output of the second latch, and the data output of the third latch is coupled to the main data output of the flip-flop cell. The inverting clock input of the first latch, the non-inverting clock input of the second latch, and the inverting clock input of the third latch are all coupled to the main clock input of the flip-flop cell.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to digital flip-flops, and, in particular, to a flip-flop which is designed to provide immunity from clock skew.

2. Description of the Related Art

Clock skew can be a major problem in the design of digital circuits having multiple flip-flops and multiple clocks, for example, in an asynchronous environment. As the number of flip-flops and/or the number of clocks increases, so does the possibility of skew being a problem. Two or more clocks can have skew between them for many reasons, including for example, that the clocks are derived from two or more unique clocks or that the clocks are from a different distribution chain for the same clock. Whatever the reason, skew frequently causes a lack of correlation between actual and predicted silicon behavior.

The destructive effects of clock skew are best illustrated by an example. Referring to FIG. 1, the Q output of flip-flop A is connected to the D input of flip-flop B. Flip-flop A receives clock X, and flip-flop B receives clock Y. FIG. 2 illustrates the operation of flip-flops A and B under ideal conditions, i.e., when there is no skew between clocks X and Y. Because flip-flops A and B are rising edge-triggered D flip-flops, the output of flip-flop A goes high 28 in response to the rising edge 20 of clock X, and the output of flip-flop B goes high 30 in response to the rising edge 22 of clock Y. In the scenario illustrated in FIG. 2, flip-flop A's output data will be transferred to flip-flop B one clock period later. For example, when flip-flop A's output goes low 32 in response to rising edge 24, flip-flop B's output goes low 34 in response to rising edge 26 one clock period later. In other words, flip-flop B takes up flip-flop A's "previous" value, while flip-flop A takes up a "new state". This is because both flip-flops A and B are updated at the same time on the rising edge of their respective clocks.

FIG. 3 illustrates the operation of flip-flops A and B when there is skew 44 between clocks X and Y. In this scenario, flip-flop B takes up the "new" value of flip-flop A as opposed to taking up the "previous" value of flip-flop A. Specifically, flip-flop A's output goes high 36 in response to the rising edge 38 of clock X, and flip-flop B's output goes high 40 in response to the rising edge 42 of clock Y.

The skew 44 between clocks X and Y causes the rising edge 42 of clock Y to trigger flip-flop B after the output of flip-flop A has already gone high 36. Because flip-flop A's output is the input of flip-flop B, the output 40 of flip-flop B, in response to rising edge 42, is the "new" value 36 of flip-flop A. In other words, because of the skew 44 between clocks X and Y, the data races through flip-flop A.

Because the existence and/or amount of clock skew tends to be unpredictable, such skew makes the behavior of flip-flop circuits unpredictable. Although FIG. 1 shows the Q output of flip-flop A being connected to the D input of flip-flop B, it will be appreciated that skew has similar "destructive" effects on any other type of connection between flip-flops A and B. For example, if the Q or Q -- output of flip-flop A is connected to flip-flop B's scan data input, asynchronous set or asynchronous reset, skew between clocks X and Y will similarly make the output of flip-flop B unpredictable. Furthermore, the problems associated with clock skew are not unique to the specific types of D flip-flops shown in FIG. 1. Specifically, flip-flops A and B are so called "scan" flip-flops which include a second "scan data" input (SI), multiplexed with the D input, which allows the flip-flop to operate as a shift register. Skew can have negative effects on the operation of any type of flip-flop, whether or not it includes set and/or reset functions, is a scan flip-flop, or is a D flip-flop.

For example, a normal scan flip flop having the multiplexed D flip-flop arrangement is referred to herein as an "SFFD", a normal scan flip flop with an asynchronous set capability is referred to herein as an "SFFDS", a normal scan flip flop with an asynchronous reset capability is referred to herein as an "SFFDR", and a normal scan flip flop with an asynchronous set and reset is referred to herein as an "SFFDRS". Table I below summarizes many of the connections between flip-flops A and B in which clock skew can create a problem:

              TABLE I______________________________________                   ConnectingFlip-Flop A's output      Flip-Flop B Type is                   with flop B's input______________________________________Data out   SFFD         Normal data                   Scan dataData out   SFFDS        Normal data                   Scan data                   Asynchronous SetData out   SFFDR        Normal data                   Scan data                   Asynchronous ResetData out   SFFDRS       Normal data                   Scan data                   Asynchronous Reset and Set______________________________________

Table I deals with connections only between scan flip-flops. Clock skew is also a problem for non-scan flip-flops having similar connections.

One specific example in which skew can have destructive effects on the operation of scan flip-flops is illustrated in FIG. 4. It is well known that the testing of an integrated circuit has become a significant part of its total cost. Thus, techniques which can simplify such testing can help to reduce manufacturing costs. FIG. 4 illustrates a portion of an integrated circuit 45 which has been designed to include features which simplify its own testing. Such circuits are often referred to as having a design for test feature, or DFT. Scan flip-flops have sometimes been used in such circuits to implement DFT.

Integrated circuit 45 includes logic circuits 46, 47. After the manufacturing process of integrated circuit 45 is complete, it may be desirable or necessary to test logic circuits 46, 47. If logic circuits 46, 47 were isolated circuit components, they could be easily tested by providing a set of inputs and verifying that the correct output data is generated. However, logic circuits 46, 47 are "buried" in the integrated circuit 45 such that direct access to their inputs and outputs is not possible, making testing of logic circuits 46, 47 difficult.

In order to provide a way to test logic circuits 46, 47, it is well known in the art to use conventional scan flip-flops 48, 49 to shift test values into the circuit 45, as well as shift the current contents of the flip-flops out of the circuit 45 in order to verify their values. For example, by using flips-flops 48, test values for the inputs of logic circuit 47 can be shifted into scan input A and the current output values of logic circuit 46 can be shifted out of scan output A. By using flip-flops 49, the current output values of logic circuit 47 can be shifted out of scan output B and test values for the inputs of the next logic circuit (not shown) can be shifted into scan input B. These shift operations are referred to as "scan shift" operations. Thus, by using the scan flip-flops 48, 49 (which have the shifting capability), rather than non-scan flip-flops, the integrated circuit 45 has been designed for testing, i.e., Scan-DFT.

The ideal environment for implementing Scan-DFT is the pure computing one, i.e., a single clock and synchronous in nature. However, for practical reasons Scan-DFT is sometimes implemented in a non-computing environment, i.e., multiple clocks and asynchronous in nature. This is the scenario illustrated in FIG. 4, and this is the environment in which clock skew becomes a problem.

Clocks A, B and C are independent clocks. If there is skew between any of them, the scan shift operation can be destroyed in the manner described above with respect to FIG. 3. In other words, certain of the flip-flops 48, 49 in the chain may take the "new" value of the immediately preceding flip-flop. This will create incorrect and meaningless data at the scan outputs A and B, thus defeating the purpose of DFT.

There have been some ad-hoc attempts to solve the skew problem, but they have generally been very silicon intensive and provided limited protection. Such attempts usually involve delaying signals to provide a certain amount of skew protection. The amount of skew protection tends to be somewhat proportional to the amount of delay, i.e., the more silicon that is used to provide delays, the more skew protection that is obtained. In an environment having a large number of clocks, the silicon cost, i.e., die area, can be very high. Thus, a trade-off must be made between skew protection and die area, and, as is common with such trade-offs, a degree of uncertainty usually remains as to whether the chosen amount of skew protection is enough.

Thus, there is a need for an apparatus and method which will solve the problems created by clock skew on flip-flop circuits.

SUMMARY OF THE INVENTION

The present invention provides a flip-flop cell having a main data input, a main data output and a main clock input. The flip-flop cell includes a first latch having a data input, a data output and an inverting clock input. The data input of the first latch is coupled to the main data input of the flip-flop cell. A second latch has a data input, a data output and a non-inverting clock input. The data input of the second latch is coupled to the data output of the first latch. A third latch has a data input, a data output and an inverting clock input. The data input of the third latch is coupled to the data output of the second latch, and the data output of the third latch is coupled to the main data output of the flip-flop cell. The inverting clock input of the first latch, the non-inverting clock input of the second latch, and the inverting clock input of the third latch are all coupled to the main clock input of the flip-flop cell.

The present invention also provides a flip-flop cell having a main data input, a main data output and a main clock input. The flip-flop cell includes a flip-flop having a data input, a data output and a clock input. The flip-flop data input forms the main data input for the flip-flop cell and the flip-flop clock input forms the main clock input for the flip-flop cell. The flip-flop is triggered in response to data on the flip-flop data input and a first rising edge of a clock received at the flip-flop clock input. A latch having a data input, a data output and an inverting clock input, has its data input coupled to the data output of the flip-flop. The inverting clock input of the latch is coupled to the clock input of the flip-flop, and the data output of the latch forms the main data output for the flip-flop cell. The latch is triggered in response to data on the flip-flop data output and a first falling edge of the clock immediately following the first rising edge received at the flip-flop clock input.

The present invention also provides a circuit having a design for test feature. The circuit includes a plurality of flip-flops each having a main data input, a main scan data input, a main data output and a main clock input. The flip-flops are arranged serially in a chain with the main data output of each flip-flop being coupled to the main scan data input of an adjacent flip-flop. Each of the flip-flops includes first, second and third latches coupled serially and successively together with the second latch being triggered in response to a first rising edge of a clock received at the flip-flop main clock input and the third latch being triggered in response to a first falling edge immediately following the first rising edge of the clock received at the flip-flop main clock input. A data input of the first latch is coupled to the main data input of the flip-flop and a data output of the third latch is coupled to the main data output of the flip-flop.

The present invention also provides a method of performing a flip-flop function. The method includes the steps of: receiving a data bit at a main data input; receiving a clock signal at a main clock input; latching the data bit with a first latch on a first falling edge of the clock signal; latching an output of the first latch with a second latch on a first rising edge of the clock signal immediately following the first falling edge; latching an output of the second latch with a third latch on a second falling edge of the clock signal immediately following the first rising edge; and transferring an output of the third latch to a main data output.

The present invention also provides a method of providing skew protection in a flip-flop having a data input, a data output and a clock input. The method includes the steps of: coupling the data output of the flip-flop to an input of a latch; coupling the clock input of the flip-flop to a clock input of a latch; generating a data bit at the data output of the flip-flop on a first rising edge of a clock signal received at the clock input of the flip-flop; latching the data bit with the latch on a first falling edge of the clock signal immediately following the first rising edge; and providing an output of the latch as an alternative to the output of the flip-flop.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating two conventional flip-flops.

FIG. 2 is a timing diagram illustrating the operation of the flip-flops shown in FIG. 1 when there is no clock skew.

FIG. 3 is a timing diagram illustrating the operation of the flip-flops shown in FIG. 1 when there is clock skew.

FIG. 4 is a schematic diagram illustrating a conventional design for test (DFT) circuit.

FIG. 5 is a schematic diagram illustrating a flip-flop in accordance with the present invention.

FIG. 6 is a timing diagram illustrating the operation of the flip-flop shown in FIG. 5.

FIG. 7 is a detailed schematic diagram illustrating another flip-flop in accordance with the present invention.

FIG. 8 is a timing diagram illustrating the operation of the flip-flop shown in FIG. 7.

FIG. 9 is a detailed schematic diagram illustrating the flip-flop shown in FIG. 5.

FIG. 10 is a schematic diagram illustrating the flip-flop cell of FIG. 5 replacing flip-flop A of FIG. 1, in accordance with the present invention.

FIG. 11 is a schematic diagram illustrating the flip-flop cell of FIG. 5 replacing all of the scan flip-flops of FIG. 4, in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 5, there is illustrated a flip-flop cell 50 in accordance with the present invention. The cell 50 has been designed to provide immunity from skew in a very cost effective and uniform/methodical manner. The cell 50 may or may not include the scan data input, set and/or reset functions, and may be used as a replacement cell, i.e., replacing conventional flip-flops, to provide the same function as the replaced flip-flop, as well as skew immunity. One-half of a clock period worth of skew immunity is provided. One advantage of this is that, assuming a user has the option to run a system at different frequencies, the one-half period of skew immunity can be as large or small as the user chooses.

The flip-flop cell 50 includes a conventional flip-flop, such as flip-flop A, and a latch 52. The latch 52 is connected to the same clock that is used to drive flip-flop A, in this case clock X, and to a data output of flip-flop A. The output of the latch 52 is the new data output for flip-flop A. The latch 52 is triggered on the falling edge of clock X.

FIG. 6 illustrates the operation of the flip-flop cell 50 when it is used to replace flip-flop A in FIG. 1, as is shown in FIG. 10. Again, clocks X and Y have a certain amount of skew 44 between them. Flip-flop A's old data output goes high 36 in response to the rising edge 38 of clock X. Flip-flop A's new data output, i.e., the output of the latch 52, does not go high 54 until the falling edge 56 of clock X. This means that the input of flip-flop B, i.e., the new data output of flip-flop A, is still low 58 on the rising edge 42 of clock Y. This prevents flip-flop B's output from going high in response to the rising edge 42 of clock Y. Instead, flip-flop B's output goes high 62 in response to the rising edge 60 of clock Y. Thus, flip-flop A's output data (from the old data output) is correctly and predictably transferred to flip-flop B one clock period later.

Flip-flop A's old data output goes low 64 in response to the rising edge 66 of clock X. This is followed by flip-flop A's new data output, i.e., the output of the latch 52, going low 70 on the next falling edge 68 of clock X. Because the input of flip-flop B, i.e., the new data output of flip-flop A, is still high 72 on the rising edge 74 of clock Y, the output of flip-flop B remains high after the rising edge 74. Thus, flip-flop B takes up flip-flop A's "previous" value, while flip-flop A takes up a "new state". Finally, one clock period later, on the rising edge 76 of clock Y, the output of flip-flop B goes low 78 because its input, i.e., flip-flop A's new data output, is low.

The flip-flop cell 50 provides normal/expected behavior despite the skew 44 between clocks X and Y. Because flip-flop A's new data output does not go high 54 until the falling edge 56 of clock X, the amount of skew immunity that is provided is equal to one-half of a clock period (or clock cycle), i.e., the period of time between the rising edge 38 of clock X and the falling edge 56 of clock X.

Referring to FIG. 7, there is illustrated a detailed schematic of a flip-flop cell 80 in accordance with the present invention. The flip-flop cell 80 is basically the same as the flip-flop cell 50 except that the "scan data" feature has been omitted. Again, it should be well understood that the teachings of the present invention apply to any type of flip-flop, including but not limited to, D flip-flops, scan flip-flops, flip-flops having set and/or reset functions, etc. In accordance with the present invention, a latch is added to the output of these flip-flops in order to provide one-half period of skew immunity.

The two latches 82, 84 form a conventional D flip-flop 86. The first latch 82 is triggered on the falling edge of clock Z, and the second latch 84 is triggered on the rising edge of clock Z. In accordance with the present invention, a third latch 88 is included. The third latch 88 is triggered on the falling edge of clock Z.

FIG. 8 illustrates the operation of the flip-flop cell 80. Initially, input D1 goes high 89. Output Q1 goes high 90 in response to the falling edge 92 of clock Z. Consequently, output Q2 goes high 94 in response to the rising edge 96 of clock Z, and output Q3 goes high 98 in response to the falling edge 100 of clock Z. When input D1 is brought low 102, output Q1 goes low 104 on the next falling edge 100 of clock Z. Consequently, output Q2 goes low 106 in response to the rising edge 108 of clock Z, and output Q3 goes low 110 in response to the falling edge 112 of clock Z.

Referring to FIG. 9, there is illustrated a detailed schematic diagram of the flip-flop cell 50. Specifically, a multiplexer 116 having two inputs has its output coupled to the latch 114. One of the inputs of the multiplexer 116 serves as the D input and the other input serves as the scan data input SI. A control input TE is used to select either the D input or the SI input of the multiplexer 116 to route data to the data input of latch 114.

One particularly advantageous application for the flip-flop cell 50 of the present invention is in the DFT circuit 45 (FIG. 4). Specifically, the flip-flop cell 50 could be used to replace all, or some, of the scan flip-flops 48, 49 in the integrated circuit 45, as is shown in FIG. 11. This would prevent any adverse effect on the scan shift operation caused by the skew between clocks A, B and C.

In general, whenever a connection between conventional flip-flops is likely to encounter a skew problem, the conventional flip-flops can be replaced by one of the flip-flop cells 50, 80. Again, a flip-flop circuit in accordance with the present invention may be a scan or non-scan flip-flop, and may or may not include set and/or reset functions, etc. The flip-flop circuits 50, 80 will provide the same function as the original replaced flip-flop, and in addition, will provide one-half cycle of skew immunity.

The inclusion of the latches 52, 88 in the flip-flop cells 50, 80, respectively, requires less silicon die area than the ad-hoc attempts to solve the skew problem discussed above. For example, Table II below summarizes the estimated increases in cell area, over conventional scan flip-flops having no skew protection, of scan flip-flops having about 4 ns of skew protection using one of the ad-hoc solutions discussed above and several variations of the scan flip-flop 50 of the present invention. As can be seen from Table II, there is a dramatic reduction in the area overhead for the cells of the present invention.

              TABLE II______________________________________Flip-Flop  Area increase for 4ns delay                  Area increase for new cell 50 ofA's type  using ad-hoc solution                  present invention______________________________________SFFD   An increase of 88%                  An increase of 36%SFFDS  An increase of 73%                  An increase of 30%SFFDR  An increase of 80%                  An increase of 33%SFFDRS An increase of 60%                  An increase of 24%______________________________________

Thus, the flip-flop cells 50, 80 of the present invention provide a less expensive and more reliable solution to the clock skew problem.

It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.

Claims (17)

What is claimed is:
1. A circuit having a design for test feature, comprising:
logic circuitry;
a plurality of flip-flop cells each having a main data input, a main scan data input, a main data output and a main clock input, the flip-flop cells being arranged serially in a chain with the main data input of each flip-flop cell being coupled to the logic circuitry, the main data output of each flip-flop cell being coupled to the main scan data input of an adjacent flip-flop cell, and the main clock input of each flip-flop cell being coupled to a different one of a plurality of independent clock signals that each have an amount of skew between them;
each of the flip-flop cells including first, second and third latches coupled serially and successively together with the second latch being triggered in response to a first rising edge of one of the plurality of independent clock signals received at the flip-flop cell main clock input and the third latch being triggered in response to a first falling edge immediately following the first rising edge of the one of the plurality of independent clock signals received at the flip-flop cell main clock input, a data input of the first latch being coupled to the main data input of the flip-flop cell and a data output of the third latch being coupled to the main data output of the flip-flop cell.
2. A circuit in accordance with claim 1, wherein each of the flip-flop cells further comprises:
a multiplexer having first and second inputs and an output, the output being coupled to the data input of the first latch, the first input being coupled to the main data input of the flip-flop cell and the second input being coupled to the main scan data input of the flip-flop cell.
3. A circuit in accordance with claim 2, wherein each of the flip-flop cells further comprises:
a control input configured to select one of the first and second inputs of the multiplexer to route data to the data input of the first latch.
4. A method of performing a flip-flop function, comprising the steps of:
providing a data bit to a main data input of a first flip-flop cell having first, second and third latches;
providing a first clock signal to a main clock input of the first flip-flop cell;
latching the data bit with the first latch on a first falling edge of the first clock signal;
latching an output of the first latch with the second latch on a first rising edge of the first clock signal immediately following the first falling edge;
latching an output of the second latch with the third latch on a second falling edge of the first clock signal immediately following the first rising edge;
transferring an output of the third latch to a main data output of the first flip-flop cell;
transferring an output of the main data output of the first flip-flop cell to an input of a second flip-flop cell;
providing a second clock signal to a clock input of the second flip-flop cell, the first and second clock signals having an amount of skew between them; and transferring the input of the second flip-flop cell to an output of the second flip-flop cell on a first rising edge of the second clock signal which follows the first rising edge of the first clock signal by a sum of one clock period and the amount of skew present between the first and second clock signals.
5. A method in accordance with claim 4, further comprising the steps of:
receiving a data bit at a main scan data input of the first flip-flop cell; and
multiplexing the main data input of the first flip-flop cell with the main scan data input.
6. A method in accordance with claim 5, further comprising the step of:
selecting between the main data input and the main scan data input of the first flip-flop cell.
7. A method of providing skew protection during a transfer of data from a first flip-flop to a second flip-flop, each flip-flop having a data input, a data output and a clock input, the method comprising the steps of:
providing a first clock signal to the clock input of the first flip-flop;
providing a data bit to the data input of the first flip-flop;
coupling the data output of the first flip-flop to an input of a latch;
coupling the clock input of the first flip-flop to a clock input of a latch;
generating a data bit at the data output of the first flip-flop on a first rising edge of the first clock signal received at the clock input of the first flip-flop;
latching the data bit with the latch on a first falling edge of the first clock signal immediately following the first rising edge of the first clock signal;
providing an output of the latch to the data input of the second flip-flop;
providing a second clock signal to the clock input of the second flip-flop, the first and second clock signals having an amount of skew between them; and
transferring data on the data input of the second flip-flop to the data output of the second flip-flop on a first rising edge of the second clock signal which follows the first rising edge of the first clock signal by a sum of one clock period and the amount of skew present between the first and second clock signals.
8. A method in accordance with claim 7, wherein the first and second flip-flops each comprise a scan flip-flop having a scan data input.
9. A method of compensating for clock skew when performing a shift operation between a first flip-flop and a second flip-flop, the method comprising:
providing a first clock signal to a clock input of the first flip-flop;
providing a second clock signal to a clock input of the second flip-flop, the first and second clock signals having an amount of skew between them;
providing a data bit to a data input of the first flip-flop;
transferring the data bit through the first flip-flop to an output of the first flip-flop on a first rising edge of the first clock signal;
providing the data bit present at the output of the first flip-flop to an input of a latch;
providing the first clock signal to a clock input of the latch;
transferring the data bit through the latch to an output of the latch in response to a first falling edge of the first clock signal following the first rising edge of the first clock signal by one-half clock period;
providing the data bit present at the output of the latch to a data input of the second flip-flop; and
transferring the data bit through the second flip-flop to an output of the second flip-flop on a first rising edge of the second clock signal which follows the first rising edge of the first clock signal by a sum of one clock period and the amount of skew present between the first and second clock signals;
wherein the data bit is prevented from being transferred through the second flip-flop on a rising edge of the second clock signal which occurs earlier than the first rising edge of the second clock signal.
10. A method in accordance with claim 9, wherein the step of providing the data bit present at the output of the latch to a data input of the second flip-flop comprises the step of:
providing the data bit present at the output of the latch to a normal data D input of the second flip-flop.
11. A method in accordance with claim 9, wherein the step of providing the data bit present at the output of the latch to a data input of the second flip-flop comprises the step of:
providing the data bit present at the output of the latch to a scan data input of the second flip-flop.
12. A method of compensating for clock skew when performing a shift operation between a first flip-flop and a second flip-flop, the method comprising:
replacing the first flip-flop with a flip-flop cell comprising a third flip-flop and a latch, a data output of the third flip-flop being connected to a data input of the latch and a clock input of the third flip-flop being connected to a clock input of the latch;
providing a first clock signal to the clock input of the third flip-flop;
providing a second clock signal to a clock input of the second flip-flop, the first and second clock signals having an amount of skew between them;
providing a data bit to a data input of the third flip-flop;
transferring the data bit through the third flip-flop to the data output of the third flip-flop on a first rising edge of the first clock signal;
transferring the data bit present at the data output of the third flip-flop through the data input of the latch to an output of the latch in response to a first falling edge of the first clock signal following the first rising edge of the first clock signal by one-half clock period;
providing the data bit present at the output of the latch to a data input of the second flip-flop; and
transferring the data bit through the second flip-flop to an output of the second flip-flop on a first rising edge of the second clock signal which follows the first rising edge of the first clock signal by a sum of one clock period and the amount of skew present between the first and second clock signals;
wherein the data bit is prevented from being transferred through the second flip-flop on a rising edge of the second clock signal which occurs earlier than the first rising edge of the second clock signal.
13. A method in accordance with claim 12, wherein the step of providing the data bit present at the output of the latch to a data input of the second flip-flop comprises the step of:
providing the data bit present at the output of the latch to a normal data D input of the second flip-flop.
14. A method in accordance with claim 12, wherein the step of providing the data bit present at the output of the latch to a data input of the second flip-flop comprises the step of:
providing the data bit present at the output of the latch to a scan data input of the second flip-flop.
15. A method of compensating for clock skew when using a first flip-flop to asynchronously set a second flip-flop, the method comprising:
providing a first clock signal to a clock input of the first flip-flop;
providing a second clock signal to a clock input of the second flip-flop, the first and second clock signals having an amount of skew between them;
providing a data bit to a data input of the first flip-flop;
transferring the data bit through the first flip-flop to an output of the first flip-flop on a first rising edge of the first clock signal;
providing the data bit present at the output of the first flip-flop to an input of a latch;
providing the first clock signal to a clock input of the latch;
transferring the data bit through the latch to an output of the latch in response to a first falling edge of the first clock signal following the first rising edge of the first clock signal by one-half clock period;
providing the data bit present at the output of the latch to an asynchronous set input of the second flip-flop; and
asynchronously setting the second flip-flop in response to the data bit being provided to the asynchronous set input of the second flip-flop during a clock period of the second clock signal which starts with a first rising edge of the second clock signal which follows the first rising edge of the first clock signal by the amount of skew between the first and second clock signals;
wherein the second flip-flop is prevented from being set during a clock period of the second clock signal which occurs earlier than the first rising edge of the second clock signal.
16. A method of compensating for clock skew when using a first flip-flop to asynchronously reset a second flip-flop, the method comprising:
providing a first clock signal to a clock input of the first flip-flop;
providing a second clock signal to a clock input of the second flip-flop, the first and second clock signals having an amount of skew between them;
providing a data bit to a data input of the first flip-flop;
transferring the data bit through the first flip-flop to an output of the first flip-flop on a first rising edge of the first clock signal;
providing the data bit present at the output of the first flip-flop to an input of a latch;
providing the first clock signal to a clock input of the latch;
transferring the data bit through the latch to an output of the latch in response to a first falling edge of the first clock signal following the first rising edge of the first clock signal by one-half clock period;
providing the data bit present at the output of the latch to an asynchronous reset input of the second flip-flop; and
asynchronously resetting the second flip-flop in response to the data bit being provided to the asynchronous reset input of the second flip-flop during a clock period of the second clock signal which starts with a first rising edge of the second clock signal which follows the first rising edge of the first clock signal by the amount of skew between the first and second clock signals;
wherein the second flip-flop is prevented from being reset during a clock period of the second clock signal which occurs earlier than the first rising edge of the second clock signal.
17. A method of testing a logic circuit with a scan shift operation which compensates for clock skew, comprising the steps of:
arranging a plurality of flip-flops serially in a first chain with a normal data input of each flip-flop being coupled to the logic circuit;
arranging a plurality of latches serially in a second chain with a data input of each latch being coupled to a data output of an associated flip-flop, a clock input of each latch being coupled to a clock input of its associated flip-flop, and a data output of each latch being coupled to a scan data input of an adjacent flip-flop;
providing a different one of a plurality of independent clock signals to the clock input of each flip-flop, the independent clock signals having an amount of skew between them;
transferring a data bit present at the scan data input of a first flip-flop in the first chain to the data output of the first flip-flop on a first rising edge of a first of the plurality of independent clock signals;
transferring the data bit present at the data output of the first flip-flop through its associated latch to an output of the associated latch on a first falling edge of the first clock signal immediately following the first rising edge of the first clock signal; and
transferring the data bit present at the output of the associated latch through the scan data input of a second flip-flop in the first chain to an output of the second flip-flop on a first rising edge of a second of the plurality of independent clock signals which follows the first rising edge of the first clock signal by a sum of one clock period and the amount of skew present between the first and second clock signals;
wherein the data bit is prevented from being transferred through the second flip-flop on a rising edge of the second clock signal which occurs earlier than the first rising edge of the second clock signal.
US08727289 1996-10-09 1996-10-09 Flip-flop cell having clock skew protection Expired - Lifetime US5774003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08727289 US5774003A (en) 1996-10-09 1996-10-09 Flip-flop cell having clock skew protection

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08727289 US5774003A (en) 1996-10-09 1996-10-09 Flip-flop cell having clock skew protection
DE1997136788 DE19736788C2 (en) 1996-10-09 1997-08-23 Circuit with test function
KR19970044695A KR100257208B1 (en) 1996-10-09 1997-08-30 Ff sel having clock skew protection

Publications (1)

Publication Number Publication Date
US5774003A true US5774003A (en) 1998-06-30

Family

ID=24922076

Family Applications (1)

Application Number Title Priority Date Filing Date
US08727289 Expired - Lifetime US5774003A (en) 1996-10-09 1996-10-09 Flip-flop cell having clock skew protection

Country Status (3)

Country Link
US (1) US5774003A (en)
KR (1) KR100257208B1 (en)
DE (1) DE19736788C2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060924A (en) * 1997-11-06 2000-05-09 Fujitsu Limited Semiconductor integrated circuit which contains scan circuits of different types
US6150861A (en) * 1998-01-09 2000-11-21 Texas Instruments Incorporated Flip-flop
US6182256B1 (en) * 1998-06-16 2001-01-30 National Semiconductor Corporation Scan flip-flop that simultaneously holds logic values from a serial load and a subsequent parallel load
US6240524B1 (en) * 1997-06-06 2001-05-29 Nec Corporation Semiconductor integrated circuit
US6300809B1 (en) 2000-07-14 2001-10-09 International Business Machines Corporation Double-edge-triggered flip-flop providing two data transitions per clock cycle
US6393592B1 (en) * 1999-05-21 2002-05-21 Adaptec, Inc. Scan flop circuitry and methods for making the same
US20070080714A1 (en) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc. Flip-flop circuit
US20130346811A1 (en) * 2012-06-21 2013-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Decision feedback equalizer
US20160188772A1 (en) * 2014-12-30 2016-06-30 Samsung Electronics Co., Ltd. Method of designing an integrated circuit and computing system for designing an integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604904B1 (en) 2004-10-02 2006-07-28 삼성전자주식회사 Flip flop circuit with Scan input

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1325677A1 *
JPS6348014A (en) * 1986-08-18 1988-02-29 Nec Corp Prescaler
US4873456A (en) * 1988-06-06 1989-10-10 Tektronix, Inc. High speed state machine
JPH01268220A (en) * 1988-04-19 1989-10-25 Seiko Epson Corp Pulse generation circuit
JPH031608A (en) * 1989-05-30 1991-01-08 Mitsubishi Electric Corp Master slave type flip-flop circuit
JPH0322610A (en) * 1989-06-19 1991-01-31 Nec Corp Synchronizing pulse generating circuit
JPH0334617A (en) * 1989-06-29 1991-02-14 Nec Corp Flip-flop circuit
US5115435A (en) * 1989-10-19 1992-05-19 Ncr Corporation Method and apparatus for bus executed boundary scanning
US5172397A (en) * 1991-03-05 1992-12-15 National Semiconductor Corporation Single channel serial data receiver
US5172011A (en) * 1989-06-30 1992-12-15 Digital Equipment Corporation Latch circuit and method with complementary clocking and level sensitive scan capability
US5210759A (en) * 1990-11-19 1993-05-11 Motorola, Inc. Data processing system having scan testing using set latches for selectively observing test data
US5347523A (en) * 1992-03-02 1994-09-13 Motorola, Inc. Data processing system having serial self address decoding and method of operation
US5390190A (en) * 1992-05-29 1995-02-14 Sun Microsystems, Inc. Inter-domain latch for scan based design
US5418481A (en) * 1993-12-10 1995-05-23 Cray Research, Inc. Repetitive signal detector for preventing thermal runaway
US5477545A (en) * 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
US5537062A (en) * 1995-06-07 1996-07-16 Ast Research, Inc. Glitch-free clock enable circuit
US5574731A (en) * 1995-02-22 1996-11-12 National Semiconductor Corporation Set/reset scan flip-flops
US5587682A (en) * 1995-03-30 1996-12-24 Sgs-Thomson Microelectronics S.R.L. Four-quadrant biCMOS analog multiplier
US5594367A (en) * 1995-10-16 1997-01-14 Xilinx, Inc. Output multiplexer within input/output circuit for time multiplexing and high speed logic
US5606565A (en) * 1995-02-14 1997-02-25 Hughes Electronics Method of applying boundary test patterns
US5619157A (en) * 1993-12-14 1997-04-08 Sony Corporation Synchronizing circuit with dynamic and static latch circuitry
US5633606A (en) * 1995-05-25 1997-05-27 National Semiconductor Corporation Scan flip-flop that holds state during shifting
US5646567A (en) * 1994-09-01 1997-07-08 Sgs-Thomson Microelectronics Limited Scan testable double edge triggered scan cell

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2787725B2 (en) * 1990-02-14 1998-08-20 第一電子工業株式会社 The timing adjustment circuit of the data clock

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1325677A1 *
JPS6348014A (en) * 1986-08-18 1988-02-29 Nec Corp Prescaler
JPH01268220A (en) * 1988-04-19 1989-10-25 Seiko Epson Corp Pulse generation circuit
US4873456A (en) * 1988-06-06 1989-10-10 Tektronix, Inc. High speed state machine
JPH031608A (en) * 1989-05-30 1991-01-08 Mitsubishi Electric Corp Master slave type flip-flop circuit
JPH0322610A (en) * 1989-06-19 1991-01-31 Nec Corp Synchronizing pulse generating circuit
JPH0334617A (en) * 1989-06-29 1991-02-14 Nec Corp Flip-flop circuit
US5172011A (en) * 1989-06-30 1992-12-15 Digital Equipment Corporation Latch circuit and method with complementary clocking and level sensitive scan capability
US5115435A (en) * 1989-10-19 1992-05-19 Ncr Corporation Method and apparatus for bus executed boundary scanning
US5210759A (en) * 1990-11-19 1993-05-11 Motorola, Inc. Data processing system having scan testing using set latches for selectively observing test data
US5172397A (en) * 1991-03-05 1992-12-15 National Semiconductor Corporation Single channel serial data receiver
US5347523A (en) * 1992-03-02 1994-09-13 Motorola, Inc. Data processing system having serial self address decoding and method of operation
US5390190A (en) * 1992-05-29 1995-02-14 Sun Microsystems, Inc. Inter-domain latch for scan based design
US5477545A (en) * 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
US5418481A (en) * 1993-12-10 1995-05-23 Cray Research, Inc. Repetitive signal detector for preventing thermal runaway
US5619157A (en) * 1993-12-14 1997-04-08 Sony Corporation Synchronizing circuit with dynamic and static latch circuitry
US5646567A (en) * 1994-09-01 1997-07-08 Sgs-Thomson Microelectronics Limited Scan testable double edge triggered scan cell
US5606565A (en) * 1995-02-14 1997-02-25 Hughes Electronics Method of applying boundary test patterns
US5574731A (en) * 1995-02-22 1996-11-12 National Semiconductor Corporation Set/reset scan flip-flops
US5587682A (en) * 1995-03-30 1996-12-24 Sgs-Thomson Microelectronics S.R.L. Four-quadrant biCMOS analog multiplier
US5633606A (en) * 1995-05-25 1997-05-27 National Semiconductor Corporation Scan flip-flop that holds state during shifting
US5537062A (en) * 1995-06-07 1996-07-16 Ast Research, Inc. Glitch-free clock enable circuit
US5594367A (en) * 1995-10-16 1997-01-14 Xilinx, Inc. Output multiplexer within input/output circuit for time multiplexing and high speed logic

Non-Patent Citations (14)

* Cited by examiner, † Cited by third party
Title
Fazal Ur Rehman Qureshi, "Declaration of Fazal Ur Rehman Qureshi" (regarding U.S. Patent Application No. 08/727,289), dated Sep. 23, 1997, pp. 1-3 and Exhibits A and B.
Fazal Ur Rehman Qureshi, Declaration of Fazal Ur Rehman Qureshi (regarding U.S. Patent Application No. 08/727,289), dated Sep. 23, 1997, pp. 1 3 and Exhibits A and B. *
Gibson and Liu, "Microcomputers for Engineers and Scientists", Prentice-Hall, Inc., 1987, pp. 103-109, no month.
Gibson and Liu, Microcomputers for Engineers and Scientists , Prentice Hall, Inc., 1987, pp. 103 109, no month. *
Harold S. Stone, "Microcomputer Interfacing", Addison-Wesley, 1982, pp. 88-100, no month.
Harold S. Stone, Microcomputer Interfacing , Addison Wesley, 1982, pp. 88 100, no month. *
Hill and Peterson, "Digital Logic and Microprocessors", John Wiley & Sons, 1984, pp. 491-493, no month.
Hill and Peterson, Digital Logic and Microprocessors , John Wiley & Sons, 1984, pp. 491 493, no month. *
Masakazu Shoji, "CMOS Digital Circuit Technology", Prentice Hall, 1988, pp. 299-307, no month.
Masakazu Shoji, CMOS Digital Circuit Technology , Prentice Hall, 1988, pp. 299 307, no month. *
National Semiconductor, "Intelligent Batteries Provide Updated Status Information, Longer Battery Life", date unknown, pp. 1-3, internet address: http://www.national.com/appinfo/lowpowervolt/brochure/8-- 9.html, no date.
National Semiconductor, Amplifier Applications, "LMC6980/84/88 Fuel Gauge & Charge Control Solution", date unknown, pp. 1-66 thru 1-71, no date.
National Semiconductor, Amplifier Applications, LMC6980/84/88 Fuel Gauge & Charge Control Solution , date unknown, pp. 1 66 thru 1 71, no date. *
National Semiconductor, Intelligent Batteries Provide Updated Status Information, Longer Battery Life , date unknown, pp. 1 3, internet address: http://www.national.com/appinfo/lowpowervolt/brochure/8 9.html, no date. *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6240524B1 (en) * 1997-06-06 2001-05-29 Nec Corporation Semiconductor integrated circuit
US6060924A (en) * 1997-11-06 2000-05-09 Fujitsu Limited Semiconductor integrated circuit which contains scan circuits of different types
US6150861A (en) * 1998-01-09 2000-11-21 Texas Instruments Incorporated Flip-flop
US6182256B1 (en) * 1998-06-16 2001-01-30 National Semiconductor Corporation Scan flip-flop that simultaneously holds logic values from a serial load and a subsequent parallel load
US6393592B1 (en) * 1999-05-21 2002-05-21 Adaptec, Inc. Scan flop circuitry and methods for making the same
US6300809B1 (en) 2000-07-14 2001-10-09 International Business Machines Corporation Double-edge-triggered flip-flop providing two data transitions per clock cycle
US20070080714A1 (en) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc. Flip-flop circuit
US7427875B2 (en) 2005-09-29 2008-09-23 Hynix Semiconductor Inc. Flip-flop circuit
US20130346811A1 (en) * 2012-06-21 2013-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Decision feedback equalizer
US8862951B2 (en) * 2012-06-21 2014-10-14 Taiwan Semiconductor Manufacturing Co., Ltd. Decision feedback equalizer
US9722818B2 (en) 2012-06-21 2017-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Decision feedback equalizer summation circuit
US20160188772A1 (en) * 2014-12-30 2016-06-30 Samsung Electronics Co., Ltd. Method of designing an integrated circuit and computing system for designing an integrated circuit

Also Published As

Publication number Publication date Type
DE19736788A1 (en) 1998-04-23 application
DE19736788C2 (en) 2000-05-31 grant
KR100257208B1 (en) 2000-05-15 grant

Similar Documents

Publication Publication Date Title
US5259006A (en) Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5041742A (en) Structured scan path circuit for incorporating domino logic
US5867409A (en) Linear feedback shift register
US6216256B1 (en) Semiconductor integrated circuit and method of designing the same
US6393592B1 (en) Scan flop circuitry and methods for making the same
US4587445A (en) Data output circuit with means for preventing more than half the output lines from transitioning simultaneously
US6570407B1 (en) Scannable latch for a dynamic circuit
US4602210A (en) Multiplexed-access scan testable integrated circuit
US5602855A (en) Integrated test circuit
US4740970A (en) Integrated circuit arrangement
US5252917A (en) Scanning circuit apparatus for test
US5481471A (en) Mixed signal integrated circuit architecture and test methodology
US6906555B2 (en) Prevention of metastability in bistable circuits
US5633606A (en) Scan flip-flop that holds state during shifting
US6070260A (en) Test methodology based on multiple skewed scan clocks
US6453425B1 (en) Method and apparatus for switching clocks presented to synchronous SRAMs
US6088821A (en) Logic circuit verification device for semiconductor integrated circuit
US6968486B2 (en) Master-slave-type scanning flip-flop circuit for high-speed operation with reduced load capacity of clock controller
US5719878A (en) Scannable storage cell and method of operation
US5717700A (en) Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing
US6696854B2 (en) Methods and circuitry for implementing first-in first-out structure
US6690203B2 (en) Method and apparatus for a failure-free synchronizer
US5978419A (en) Transmitter and receiver circuits for high-speed parallel digital data transmission link
US5900753A (en) Asynchronous interface
US6904553B1 (en) Deterministic testing of edge-triggered logic

Legal Events

Date Code Title Description
AS Assignment

Owner name: NATIONAL SEMICONDUCTOR CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:QURESHI, FAZAL UR REHMAN;PERSON, MARTIN WILLIAM;REEL/FRAME:008696/0584

Effective date: 19970819

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12