SU1338033A2 - Pulse sequence checking device - Google Patents

Abstract

The invention can be used in discrete message transmission systems and serves to increase the reliability of monitoring. The device contains triggers 1, 8 and 9, the elements AND 2,3,10,11,12, the elements OR 4 and 6 and the element 13 delay. An I-PI element 16 and an I-17 element are introduced into device I. The accuracy of the malfunction determination depends on the choice of the counting coefficient of the counter 15 and the frequency of the high-frequency cycles. By the number of pulses at the output of the device, one can judge the duration of the absence of pulses in one of the clock sequences. At the same time, by the presence of high-frequency pulses at the output of the device, a simultaneous absence of pulses in both clock sequences is judged. 1 il. slhh

Description

 13

The invention relates to a pulse technique and can be used only in discrete communication systems and is the perfection of a known device, which has been installed in the auth. No. 1175029.

The purpose of the invention is the new reliability of the control.

The drawing shows a structural electrical circuit for controlling a pulse train.

The device contains a trigger 1, the elements And 2 and 3, the element OR 4, the first bus 5, the element SRI 6, the second input bus 7, the triggers 8 and 9, the elements 10-12, the delay element 13, the output bus 14, the counter 15 ittulses, element OR 16, element 17, the third input type 18.

The first and second inputs of the element OR 4 are connected 1-1 with the outputs of the first 2 and second 3 elements, the first inputs of which are connected respectively to the direct and inverse outputs of the first trigger 1, the second input of the element 2 is connected to the input bus 7 , the first and second inputs of the second element OR 6 coentnieimi respectively with the outputs of the third II and fourth 12 elements AND, the first inputs of which are connected respectively to the direct outputs of the second 8 and third 9 triggers, the clock inputs of which are connected respectively to the bus 5 and to the output of the electric OR 4 and with the second inputs of AND II and 12 elements, the input bus 7 is connected via a delay element 13 to the second input of the AND 3 element, the input bus 5 to the installation input of the trigger 9 and to the first input AND 10, the BTopoii input is connected to the installation the trigger input of the VIS by the output of the CHI 4 element, the output of the li 10 element is connected to the clock input of the trigger 1.

The output of the sixth element And 17 is connected to the third input of the second element OR 6, the first input of the element And 17 is connected to the output and the V-input of the pulse counter 15, the second input of the And element 17 is connected to the third input bus 18 and the clock C-input of the pulse counter 15 The installation R-input of which is connected to the output of the third element OR 16, the first input of which is connected to the output of the first input element 1 school 4, and the second input / 1 connected to the second input bus oil 5.

; The device works as follows.

When the supply voltage is turned on, the triggers 8 and 9 and the counter 15 are set to the zero state (K), their outputs are low potential). Depending on the state of trigger 1, one of the inputs of the element OR 4 receives a pulse of the first clock sequence from the output of the element AND 2

And) or a delayed pulse from the output of the element AND 3. From the output of the element OR 4, this pulse arriving at the installation No. 1 input of the trigger 8 confirms its initial state and, at the counting 0 input, decays the trigger 9 into the single state. At the output of the element And 12 impulse does not pass. Also, this impulse goes to the element RSH 16 and further to the installed

 The R input is counter 15. Counter 15 is set to the initial (zero) state. On the clock C-input of the counter 15 and on the element And 17 with the third input - HOSI bus 18 high-frequency pulses

30 served continuously. The counting coefficient of the counter 15 is selected so that the signal (high potential) at the output of the counter appears when there is no installation at its R input

b time

following the impulses on the input spikes 5 and 7. Therefore, the high-frequency pulses at the output of the AND element are not passed if the input buses 5

40 and 7 are clock sequences.

A pulse of the second clock sequence arrives in time, which, according to the setup input

41, triggers the trigger 9 to the zero state and, on the counting input, decays the trigger 8 to the unit state. At the output of the element And the signal does not pass. Also this impulse through

50, the OR element 16 is fed to the R input of the pulse counter 15 and again sets it to its initial state.

And in a similar way the device works after installation, if the first

 comes the impulse of the second clock sequence, and then the first.

Thus, during normal operation of the device-a with the outputs of the elements And 11, 12 and 17, the signals fail to exit 13

Bus 14 is not received. If after switching on the power supply or during the operation period during the control of the pulse sequence, due to the instability of the generators, forming clock sequences, an overlap (in coincidence) of the signals at the inputs of the AND 10 element occurred, then in this case a signal is generated on the AND 10 element which, at the counting input, translates trigger I to the opposite state, i.e. the pulse of the second clock sequence is compared with the first pulse of the same sequence, coming from the output of the corresponding element AND (2 or 3), the second input of which receives the enable signal from the output of trigger I. Since the signals separated in time are now compared, This device operates according to the principle described above so there is no signal on the output bus.

If a pulse has not been formed in the first clock sequence, the output of the OR 4 element is also absent. Since at this moment the trigger 8 is in the single state, the next pulse of the second clock sequence leads to the appearance of the signal at the output of the AND 11 element, and consequently, the output of the OR 6 element to the output bus 14 will receive a Failure signal.

The device operates in the same way in the case of the disappearance of the pulse of the second clock sequence. Only in this case the signal of failure to the output bus 14 goes through the element OR 6 from the output of the element 12.

When the sequence of several pulses of the first (second) clock sequence disappears, the pulses of the second (first) clock sequence — a fault on the output bus 14 arrive during the entire time of the disappearance of the pulses on the input bus 7 (5). After the restoration of the first (second) clock sequence of the device Order 4143/54 Circulation 901 Subscription Production-Polygr pr-tie, Uzhgorod, ul. Project, 4

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in ceases to issue a signal Fault on the output bus 14.

 With simultaneous disappearance of pulses in both clock sequences, triggers 8 and 9 prohibit signals from passing (fighting through elements II and 12.) The pulses of installation on the R input of counter I5 from the output of element OR 16 are absent, and therefore, the counter is filled with 15 pulses from the bus 18. The signal from the output of the counter 15 enters its V-input, prohibiting further counting, also allows the passage of high-frequency pulses from the clock bus 18 through the element I I7 to the third input of the element OR 6 and further as a signal Failure to the output bus 14 Accuracy (speed) of determining the fault depends on the choice of the counting coefficient of the counter 15 and the frequency of the high-frequency clock. The accuracy increases with increasing frequency. By the number of pulses at the device output, one can judge the duration of the absence of pulses in one of the clock sequences, and pulses can be judged by the simultaneous absence of pulses in both clock sequences.

Claims (1)

Invention Formula A device for controlling a pulse sequence according to aut. St. i- I 75029, characterized in that, in order to increase the reliability of the control, a pulse counter, a third I1Sh element and a sixth AND element, whose output is connected to the third input of the second OR element, are entered, are connected to the output and the blocking input of the pulse counter, and the second input is connected to the third input bus and the clock input of the pulse counter, the setup input of which is connected to the output of the third OR element, the first input of which is connected to the output of the first OR element, and the second is connected to the first input bus.