SU1157700A1 - Clock synchronizing device - Google Patents

Abstract

A COLLATED SYNCHRONIZATION DEVICE containing a multiplier, a delay line and a series-connected low-pass filter, a controlled oscillator, a gating and reset control unit and an integrator, characterized in that, in order to improve noise immunity, a series-connected rectifier, switch, inverter and the adder, with the multiplier output through the integrator connected to the rectifier input, the switch output through the delay line connected to the corresponding input of the adder, the output of which It is connected to the input of the low-pass filter, the output of the controlled oscillator is connected to the input of the reference signal of the multiplier, and the output of the gating and reset control unit is connected to the control input of the switch.

Description

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The invention relates to radio engineering, in particular, to specialized means of receiving devices for synchronizing a receiver with a received discrete signal that does not contain specific synchronization information.

A clock synchronization device is known comprising a multiplier, a delay line and a low-pass filter connected in series, a controlled oscillator, a gating and reset control unit and an integrator, the output of which is connected to one of the multiplier multipliers through another serially connected limiter and transition detector the output of the additional integrator is connected via a series-connected analog-to-digital converter and a delay line, the integrator input being bedinen with additional input of the integrator and is an input device and an output control unit gated and discharged is connected to the additional control input of the integrator 1.

However, the known device has low noise immunity at small values of the signal-to-noise ratio at the input (under conditions of strong additive noise).

The purpose of the invention is to improve noise immunity.

The goal is achieved in that a clock synchronization device containing a multiplier, a delay line and a series-connected low-pass filter, a controlled oscillator, a gating and reset control unit and an integrator are connected in series to a rectifier, a switch, an inverter and an adder, while the output .the multiplier through the integrator is connected to the input of the rectifier, the output of the switch through the delay line is connected to the corresponding input of the adder, the output of which is connected to the input of the filter the low frequencies, the output of the controlled oscillator is connected to the input of the reference signal of the multiplier, and the output of the gating and reset control unit is connected to the control input of the switch.

FIG. 1 shows a structural electrical circuit of a clock synchronization device, n “FIG. 2 - timing diagrams for the operation of the proposed device; in fig. 3 - discriminatory characteristic of the device.

The clock synchronization device includes a multiplier 1, an integrator 2, a rectifier 3, a switch 4, a delay line 5, an inverter 6, an adder 7, a low-pass filter 8, a controlled oscillator 9, and a gate and reset control unit 10.

The device works as follows.

A random bipolar signal arrives at the device input, the duration of the symbols T of which is constant, and the value of the delay over the clock frequency is unknown. It is necessary to achieve the synphasicity of the signals of the controlled oscillator 9 and the received informational one, i.e., to perform clock synchronization. For this, the received signal (Fig. 2a) is multiplied in the interleaver 1 by the meander signal Si (t) (Fig. 26) whose duration is equal to

2; t / 4,

g The output signal of multiplier 1 is integrated by integrator 2 with a reset, which is controlled by a strobe-reset signal (Fig. 2c), whose period is equal to T / 2.

The signal from the output of the integrator 2 (Fig. 2d)

0 in the absence of noise (counts at the moments of reading) is rectified by rectifier 3 and fed to input 4 of the switch, to the control input of which the meandering signal S2 (t) is fed, the symbol duration of which is T / 2 (Fig. 2e). With a positive control signal, the information signal from the input of switch 4 passes to the first output, and to a negative output, to the second output.

0 From the time diagrams it is clear that

the synphasic signals of the gating-reset Si (i) and S2 (t) for the selection of the clock frequency of the received signal, it is necessary to ensure the synphase of the received signal and the lowest frequency of signals

control SG (t). Line 5 delay delays the signal at time T / 2. The signal at the first output of the switch 4 is shown in FIG. 2e, at the second exit - in FIG. 2g at the inputs of the adder 7 - in FIG. 2h, on

0 output of the adder 7 - in FIG. 2k

The pulse signal from the output of the adder 7 is smoothed by the low-pass filter 8 and changes the frequency of the controlled oscillator 9, the output of which is S2 (t). When reducing the time delay between the received and the reference (at the output of the controlled generator 9) signals, the form of the voltage at the output of the adder remains the same, but the amplitude decreases in proportion to the error time, providing a continuous adjustment of the frequency of the signal at the output of the controlled generator 9.

The quantitative characteristic of noise immunity is understood as the magnitude of the error at the output of the device, provided at certain values of the signal-to-noise ratio at the input and the error between the input and reference signals. In this case, the equivalent linearized circuits of the proposed and known devices differ only in the magnitude of the gain of the tracking system (the slope of the discriminator). The steepness of the characteristics of the discriminator of the proposed device on the interval (-T / 4, T / 4) is

to -

 - - "

UthGTS

where K is the number of changes in the sign of the received signal per second; fmax is the clock frequency of the received signal.

Using this ratio, one can determine the gain in noise immunity of the proposed device, the value of which at various values of the input and reference signal mismatch is characterized by the value ./T, where is the normalized error value (Fig. 3). For the mismatch values of the input and reference signals / T 0.3, the noise immunity of the proposed device rises almost 3 times compared to the known one when the signal-to-noise ratio at the input J) is 1 and more than 2 times at J 4.

Claims (1)

TACT SYNCHRONIZATION DEVICE, comprising a multiplier, a delay line and a series-connected low-pass filter, a controlled generator, a gating and reset control unit and an integrator, characterized in that, in order to increase noise immunity, a series-connected rectifier, switch, inverter and adder are introduced into it , while the output of the multiplier through the integrator is connected to the input of the rectifier, the output of the switch through the delay line is connected to the corresponding input of the adder, the output of which is for prison to the input low-pass filter controlled oscillator output is connected to the multiplier input of reference signal and the output of the control block gating and reset switch connected to the control input. Figure 1 SU ..., 1157700