SU1449961A1 - Apparatus for synchronizing seismic receivers - Google Patents

Abstract

This invention relates to electrical survey equipment. The purpose of the invention is to reduce the synchronization clock. The device contains an amplifier, N + 1 integrators, a multiplexer, a demultiplexer, a zero integrator unit, the first and second threshold devices, the first and second, swarm controlled sources of the reference voltage, the first and second D-triggers, OR circuit, block generation of synchronization pulses, a control pulse generator, a frequency multiplier, a counter, a Lix1 unit, an AND circuit. The amplifier output is connected to the integrator input and to the first input of the fixing unit, the integrator outputs are connected to the multiplexer inputs, It is connected to the non-inverting input of the first threshold device and, and) with the 1 inverting input of the second threshold device. The outputs of the first and second threshold devices are connected to the D-inputs of the first and second D-flip-flops, the outputs of which are connected to the inputs of the OR circuit, and the output of the OR circuit is connected to the input of the synchronization pulse shaping unit. The generator output of the control pulses is connected to the input of the frequency multiplier and the second input of the fixing unit. The first and second outputs of the fixing unit are connected to the inputs of the first and second controlled sources of voltage, respectively. The third output of the fixing unit is connected to the first input of the circuit I, the second input of which is combined with the input of the zero block of the integrator, the counter input and connected to the output of the frequency multiplier. The code output of the counter is connected to the control inputs of the multiplexer and demultiplexer, and the overflow output is connected to its installation input. The output of the zero integrator setup unit is connected to the input of a demultiplexer, the outputs of which are connected to the zero inputs of the integrator. The outputs of the first and second controlled voltage sources are connected respectively to the inverting input of the first threshold device and the non-inverting input of the second threshold device. The output of the circuit AND is connected to the C-input of the first and second D-flip-flops. 1 hp f-ly, - 3 ill. and $ (L with so about

Description

one

14 / -i99f)

The invention relates to technical physics, in particular, to geoelectro-exploration equipment, and can be used for autonomous synchronization of induced-polarization (VP) meters.

The purpose of the invention is to reduce synchronization errors.

FIG. 1 shows the structure of the synchronization device for electrical receivers; in fig. 2 - block diagram block diagram; in fig. 3 is a block diagram of a sync pulse shaping unit.

The synchronization device for electrical receivers includes an amplifier 1, an integrator 2, a block 3 of an integrator zero setting i, and

in the form of a standby multivibrator, the first 4 and second 5 threshold devices, the first 6 and the second 7 controlled ISTs of the reference voltage S I. the first 8 and the second 9 D-triggers 10, unit P forming them; synchronization pulses, 12 control pulse generator.

The output of amplifier 1 is connected to; the signal input of the integrator 2, D-I, the inputs of the first 8 and second 9 D-flip-flops I are connected to the outputs of the first 4 I and second 5 threshold devices, the outputs of the first 8 and second 9 D-flip-flops are connected to the first and the second input of the OR 10 circuit, the output of which is connected to the input of the synchronization unit 11 of the synchronyyra pulses, the outputs of the first 6 and second 7 controlled sources of reference voltage are connected respectively to the inverting input of the first threshold device 4 and the second non-inverting input of the second threshold device 5.

The device also contains additional integrators 13–15, multiplexer 16, demultiplexer 17, frequency multiplier 18, counter 19, fixing devices, circuit 21, Signal inputs of integrators 13–15 are connected to amplifier 1 output, integrator zero inputs 2 and 13-15 are connected to the outputs of the demultiplexer 17, the input of which is connected to the output of block 3 of the zero installation of the integrator, the inputs of the multiplexer, pa 16 are connected to the outputs of integrators 2 and 13-15, and the code of the multiplexer 16 is connected to the non-invert of the first threshold

five

0 with about

d

five

12

device 4 and the inverting input of the second threshold device 5, the output of the generator 12 control pulses connected to the input of the frequency multiplier 18 and the second input of the fixing unit 20. The first input of which is connected to the output of the amplifier 1. The first and second outputs of the fixing unit 20 are connected respectively to the inputs of the first 6 and second 7 controlled sources of the reference voltage, and the third output to the first input of the circuit 21, the second input of which is combined with the input of the integrator unit zero setting 3, the input of the counter 19 and connected to the output of the smart Residents of 18 cha simplicity. The main output of counter 19 is connected to the control input of multiplexer 16 and demultiplexer 17, and the overflow output of counter 19 is connected to its setup input. The output of circuit 21 is connected to the C-inputs of the first 8 and second 9 D-flip-flops,

The fixing unit 20 comprises a series-connected integrator 22 and a key 23, a series-connected maximum-voltage detector 24 and a first analogue storage device (AMC) 25, and a series-connected detector.

26 a maximum of a negative voltage and a second CCD 27, a serially connected frequency divider 28, a counter 29 and a trigger 30, as well as a waiting multivibrator 31 and a delay element 32. The output of the standby multivibrator 3 is connected to the zeroing input of the integrator 22, and the input is combined with the control input of the switch 23 and connected to the output of the frequency divider 28, the Output.Telement 32 of the delay is connected to the reverse voltages of the detector 24 of the maximum positive voltage

and detector 26 of the maximum negative voltage, and the input is combined with the recording inputs of the first 25 and second

27AZU and connected to the output of the counter 29..

The installation input of the counter 29 is connected to its output. The input of the integrator 22 and the input of the splitter 28 frequency serve respectively the first and second inputs of Shock 20 latching, and the outputs of the first 25 and second 27 AZS, as well as the OUTPUT of the trigger 30 serve as the first, second and third outputs of the fixing unit 20, respectively.

The synchronization pulse shaping unit 11 comprises a series-connected reference frequency generator 33 and a first counter 34, a second counter 35 connected in series, and a programmable permanent memory (PROM) 36, as well as a comparison circuit 37 and a pulse shaper 38. First LOG IN

37 comparison is connected to the output of the first counter 34, and the second input to the output of the EPROM 36. The output of the imager

38 pulses connected to set14499614

closes the AND 21 circuit. From the output of the rator 12 control pulses to the second input of the fixing unit 20 and to g multiplier 18, there are pulses with a period Tn extracted from the stationary harmonic interference having a period Tn.

After time t, 2 (), where 10 and the pulse duration of the polarizing current, tf, is the duration of the pause between pulses, from the first and second codes of the fixing unit 20 to the inputs

 .khod. ™, „heres ™, 1 С 35, s Г„: Г:,.

“:: ™:;: Pa4SPo: RT: ™ r ™ - ™ ™ - Shaper 38 input. The pulses are combined with the control input of the EPROM 36 and serves as the input of the synchronization pulse shaping unit 11. The output of the comparison circuit 37 is connected to the input of the second counter 35 and serves as an output of the synchronization pulse shaping unit II.

Pulse generator 38 may be implemented as a differentiating cell, separating the leading and trailing edges of the input pulse,

thirty

The generator 12 control pulses contains a series-connected receiving line interference, performed in the form of an open line (antenna), a narrow-band filter and a gain of 1 G (1 g

the transmission voltage under the action of the probe pulse current of positive polarity, Ufll) - voltage

20 transmissions under the action of a negative current probe pulse.

Managed sources 6 and 7 of the reference voltage produce reference

25 voltages U and Uj, equal

,;,

where is the relative detection threshold, 0 p 1.

Managed sources 6 and 7 reference ex. can be performed on the basis of an op-amp with feedback, ensuring

 T 18 h. transfer ratio of 7. The station contains a phase detector connected to a closed circuit at the third output of a block 20, a zing filter at the same time appears low-pass, controlling a logical 1 H Le generator and a frequency divider. Output controlled by-. And 2. opening circuit

40

The GO generator serves as the output of a frequency multiplier 18, the input of which is the second input of the phase detector.

The device works as follows.

The input signal of the device is the voltage from the output of the primary converter (measuring line MN), which is an adherent

The input signal, amplified by amplifier 1, is integrated by the integrator t} and 2 and 13–15 over time intervals equal to Tf. -Tf ,, where Tp is the period of stationary gar ununicheskogo interference. 45 By choosing the multiplication factor of the multiplier 18 frequency equal to the capacity of the counter 19 and equal to N + 1, where N is the number of additional integrators, management is provided.

Noise disturbance. In general, broadband noise can also act on the input.

The input signal, amplified by the accelerator 1, is fed to the integrators 2 and 13-15, as well as to the block 20 4xxation. The initial moment of time from the third output of the fixing unit 20 is received. The signal of logical O, which

Because the integration intervals specified by the output signal of the integrator zeroing unit 3 under the influence of the frequency multiplier 18 signal, 55 are shifted in time relative to each other by the value of TC / N + lC using multiplexer 16, controlled synchronously with the demultiplexer 17 by the same counter 19, the output Signal ™ ™ - 0

  (1g

the transmission voltage under the action of the probe pulse current of positive polarity, Ufll) - voltage

0 transmission under the action of a probe current pulse of negative polarity.

Managed sources 6 and 7 of the reference voltage produce reference

5 voltages U and Uj, equal

,;,

where is the relative detection threshold, 0 p 1.

Managed sources 6 and 7 reference ex. can be performed on the basis of an op-amp with feedback, ensuring

transfer ratio of 7. At the third output of the unit 20, xaxing at the same time appears logical 1 × Le And 2. The opening circuit

40

The input signal, amplified by amplifier 1, is integrated by the integrator t} and 2 and 13–15 over time intervals equal to Tf. -Tf ,, where Tp is the period of stationary gar ununicheskogo interference. 45 By selecting the multiplier of the multiplier 18 frequency equal to the capacity of the counter 19 and equal to N + 1, where N is the number of additional integrators, is provided by the control: g, g

 .: „, G - g

Because the integration intervals specified by the output signal of the integrator zeroing unit 3 under the influence of frequency multiplier 18 are shifted in time relative to each other by the value of TC / N + lC using multiplexer 16, controlled synchronously with demultiplexer 17 with the same counter 19, output signals M integragors 2 and 13-15 for the time TL / N + 1 before the end of the integration interval are connected to the non-rotating input of the threshold device | of device 4 and to the inverting input of threshold device 5. The multiplex 16 and demultiplex er 17 may. ° be performed based on the integral circuit K590 KHI.

The output logic signals of threshold devices 4 and 5 are formed according to the following laws:

if UK-U is 0-, if 0; and ,, if ul-un 0; H, 0, if Uo -Uu Oh ,.

14499616

the driving current pulse, the voltage across the integrators 2 and 13-15 over the integration interval increases,

The output voltage of the integrator 14 on the interval t exceeds the reference voltage Ut, therefore at the moment of time t ffj the D-trigger 8 is set-g

poured into

T

that svid telst15

1Q argues about detecting the leading edge of the current probe pulse.

After switching off the current probe pulse (time tj) as 5 the overlap range of the integration intervals and the probe current pulse decreases, the voltage at the outputs of integrators 2 and 13-15 also decreases, and at the integration interval T f4 G the voltage the output of the integrator 14 becomes less and. Therefore, the D-flip-flop 8 at the time t is set to O indicates that the trailing edge of the sensing current pulse is detected.

iffle - output logic signals of threshold devices 4 and 5 ;.

 the output of integrators 2 and 13-15.

With the help of pulses arriving at the output of the multiplier 18, the frequency with 1 |) iodine Tft / N + 1, the output logical foundations of the threshold devices 4 and 5 1 are recorded in the B-flip-flops, 8. and 9.

In the case when the input set | There is only a stationary-1Crna harmonic interference, and on a clear signal (pause), the output Signal of the integrators 2 and 13-15 is due to

integration interval is

2P

1- А sin (lii ч-4 Jdt О, --Ln

tn

de an integration interval equal to the period of a stationary harmonic interference; 40 transitional characteristics of EPs in a - constant time integral times after switch 2 and 13-15; no current. H o - the initial phase of the stationary — Fixation unit 20 works as follows. harmonic interference; shimm way. A - stationary amplitude

harmonic interference, so the D-triggers 8 and 9 when

45

From the output of the amplifier 1, the first input of the fixing unit 20 receives an additive mixture of the useful signal and interference, in particular, stationary harmonic interference, the input signal is set to O, which indicates the absence of the current-sensing current pulse.

When a probing current pulse is applied to the test medium (time: time t), a useful signal is present at the input of the device with the help of a power line and a harmonic interference that is stationary.

As more and more Part of the integrator integration interval. 2 and 13-15 falls on the zone

T

that svid telst

It is about detecting the leading edge of a current probe pulse.

After switching off the current probe pulse (time tj) as 5 the overlap range of the integration intervals and the probe current pulse decreases, the voltage at the outputs of integrators 2 and 13-15 also decreases, and at the integration interval T f4 G the voltage the output of the integrator 14 becomes less and. Therefore, the D-flip-flop 8 at the time t is set to O indicates that the trailing edge of the sensing current pulse is detected.

Similarly, the leading and trailing edges of the probing current pulse of negative polarity are detected at time t g and.

The output signals of D-triggers 8 and 9 are fed through the ISh 10 circuit to the block 1I of the generation of synchronization pulses, which generates the necessary synchronization pulses, under the influence of which the synchronized meter measures the transmission voltage during the action of the current probe pulse and the voltage

shimm way.

From the output of the amplifier 1, an additive mixture of the useful signal and interference, in particular stationary harmonic interference, is fed to the first input of the fixation unit 20, the input signal is integrated into the integral 22 at the time interval LI. The duration of the integration interval ATi is determined by the coefficient o (dividing the frequency divider 28, the input of which receives a pulse sequence with a period Tn from the output of the generator 12 control pulses, therefore

ttc) 4tp.

Coefficient (X division is selected from the condition

o (fu / 2,

on the one hand, this provides deep suppression of the stationary harmonic interference due to the multiplicity of the integration interval for the stationary harmonic interference, and on the other hand, the loss of at least one full ATU integration interval for the duration of the current probe pulse. Resetting the integrator 22 is accomplished by the output of the standby multivibrator 31, which is triggered by output pulses at the output of frequency divider 28. The output signal of the integrator 22 at the end of the interval-integration DTN is connected with a key 23 to the inputs of the detector 24 of the maximum voltage positive and the detector 26 of the maximum negative voltage, which after passing the pulses of the probing current of positive and negative polarity fix the voltage Unp and Unp respectively . At the time interval Ser 2 ((), given by the capacity of the counter 29, the output voltages of the detector 24 of the maximum positive voltage and the detector 26 of the maximum of the negative voltage are copied to the AMS 25 and 27. under the influence of a pulse, which is absorbed by the counter 29. In addition, the pulse extracted by the counter 29 sets the trigger 30 to state 1, and after a while determined by the delay element, the detector 24 of the maximum positive voltage and the detector 26 of the maximum voltage negative force zero. Nation work fixing unit 20 knots is repeated.

Thus, fixing unit 20 generates a Jjogic 1 signal at time D jp after switching on at the third input, and at the first and second outputs, values of Unp and Unp voltages which are refined, as far as possible, by changes in the input signal the instability of the current source of the generator set, as well as changes in the voltage of self-polarization of the receiving electrodes.

The pulse forming unit I1 of synchronization operates as follows.

The output signals of D-flip-flops 8 and 9, logically combined using the OR 10 scheme, are fed to the input of the synchronization pulse generation unit 11, under the influence of which 10 pulse generator 38 pulses at time 2, -4, and 4 produces short pulses. The first impulse at time tq from the output of the imaging unit 38 starts the reference frequency generator 1533, and the counters 34 and 35 are reset.

In the counter 34, a code is recorded under the influence of reference frequency pulses Q proportional to the current time of action of the probe pulse | current, which is fed to the first input of the comparison circuit 37. The second gate of the comparison circuit 37 receives the 5 code from the output of PGOU 36, which is proportional to the specified moment of measurement of the transmission voltage. At the moment of equality of the codes, the comparison circuit 37 generates a pulse, which Q arrives at the output of the synchronization pulse shaping unit 1 to start the synchronized meter, a 1-1 pulse from the output of the pulse shaper 38 at the moment of time Gl is reset to the initial state of the counter 34 and 35. point ta, the counter 34 begins to accumulate a code proportional to the pause time. Under the influence of the input Q signal at the input of the driver I of the synchronization pulses, which is equal to O on the time interval Г-fs, codes which are proportional to the moments of measuring the voltage of the transient characteristic of the VP will be gained from the PROM 36. The sequence of the choice of the measurement moments of the direction Ug from the EPROM 36 determines the counter 35, giving the code to the address input of the EPROM 36,

50

At the moment of equality of the codes, the circuit 37 generates a pulse arriving at the output of the synchronization pulse generation unit I1, as well as the input signal to the counter 35, which increases its code by selecting from the PROM 36 a regular code proportional to the next moment of measuring the VP voltage. Over time, the operation of all the nodes of the Pulse Forming Unit 11 is synchronized. The generator 12 control pulses operates as follows.

At the input of the receiving line interference,: performed in the form of an open line (antenna), there is a stationary harmonic interference, which has the same frequency as the stationary harmonic interference on the measuring line MN, but it differs in level and initial phase shift .

Accepted by the receiving interference line A stationary harmonic interference, a narrowband filter tuned to the frequency of a stationary harmonic interference, is amplified by an amplifier-limiter, after which it is inverted into a stream of rectangular pulses with a period of To is output to the generator 12: control: pulses.

I The frequency multiplier 18 works in a pleasing way.

I A periodic sequence of pulses with a period Tg is sent to the second input of the phase detector To the first input of the phase detector, jpa, from the output of the frequency divider n: rectangular pulses of the type are output. Meander with a period of following TD. Frequency multiplier 1b is a classic phase-locked loop, therefore, in the steady-state operating mode, the beer has a T ratio and, therefore, the run-time signal of the | 8 frequency knob is equal to T / K, where | cd is the divider division factor. frequencies.

Thus, the introduction of N additional integrators 13-15, multiplexer 16, demultiplexer 17, frequency multiplier 18, counter 19, fixing unit 20, and And 21 schemes and new connections allows reducing the time interval for evaluating the input signal without reducing the length of the integration interval integrators 2 and 13-15, which is determined by the stagnar harmonic interference perid, and also ensures that the reference voltages track changes in passbanding, keeping the relative detection threshold constant, which allows l average error synchronization and standard deviation

five

0

synchronization error from average.

Claims (1)

1. Synchronization device for electrical receivers, containing a power amplifier, integrator, integrator zero setting unit, first and second threshold devices, first and second controlled voltage sources, first and second D-triggers, OR circuit, sync pulse shaping unit, generator control pulses, while the amplifier amplifier is connected to the signal input of the integrator, the D-inputs of the first and second D-flip-flops are connected to the outputs of the first and second threshold devices, the outputs of the first and second D-three the germs are connected to the first and second inputs, the SHS circuit, the output of which is connected to the input of the synchronization pulse-generating unit, the outputs of the first and second controlled voltage sources are connected respectively to the inverting input of the first threshold device and the non-inverting input of the second threshold device, which is different In order to reduce synchronization errors, K-integrators, multiplexer, demultiplexer, frequency multiplier, counter, fixing unit, AND circuit, with The signal inputs of the additionally inputted integrators are connected to the amplifier output, the integrator zeroing inputs are connected to the demultiplexer outputs, the input of which is connected to the output of the integrator zero setting block, the multiplexer inputs are connected to the integrator outputs, and the multiplexer output is connected to the non-inverting input of the first threshold device and the inverting input of the second threshold device, the output of the control pulse generator is connected to the input of the frequency multiplier and to the second input of the block Aschte, the first input of which is connected to the output of the amplifier, with the first and second outputs of the unit g fixations are connected respectively to the inputs of the first and second controlled sources of the reference circuit, and the third output to the first input of the AND circuit, the second input of which 0 five 0 five 0 combined with the input of the zero-set block of the integrator, the counter input and connected to the output of the multiplier of the clock; the code-output of the counter is connected to the control input of the multiplexer and demultiplexer, and the overflow output of the counter is connected to its setup input; And connect with the C-inputs of the first and second D-flip-flops. 2, A device according to Claims 1, characterized in that the block (the fixation comprises a series-connected integrator and a key, a series-connected maximum positive voltage detector and a first analog memory, a series-connected maximum voltage detector negative and a second analog memory device, in series connected frequency divider, counter and trigger, as well as waiting mul449961 12 while the output of the standby multivibrator is connected to the zeroing input of the integrator, and the input is combined with the control input of the key and connected to the output of the frequency divider, while the output of the delay element is connected to the reverse outputs of the detector of the maximum positive Q and a maximum voltage detector of negative voltage, and the input is combined with the recording inputs of the first and second analog storage devices and connected to the meter output 15 of the counter, while the installation input of the meter is connected to its output, When this input of the integrator and the input of the frequency divider are respectively first and second inputs of block 20 fixings, and the outputs of the first and second memory devices, as well as the output of the trigger, serve respectively the first, second, and third outputs of the fixing unit. AND 01 / 2.1 .2 9g