SU1109913A1 - Digital frequency synthesizer - Google Patents

Abstract

1. A DIGITAL SYNTHESIZER OF FREQUENCIES, which contains a looped controlled oscillator, a frequency divider with a variable division factor, a frequency-phase detector and a low-pass filter, as well as a series-connected reference oscillator and a frequency divider with a fixed division factor, characterized by the fact that in order to increase speed when changing the output frequencies, between the first output of the frequency divider with a fixed division factor and another input of the frequency-phase detector are introduced sequentially with a single digital phase discriminator, the first and second elements NAND, as well as the third NAND element, the first input of which is connected to the second output of the digital phase discriminator, the output of the third NAND element is connected to the other input of the second NAND element, the second the input element of this NAND and the second input of the digital phase discriminator are combined and connected to the second output of a frequency divider with a fixed division factor, the first output of which (A is also connected to another input of the first NAND element, and the output of the frequency divider from belt-dividing ratio is also connected to the third input digital discriminator.

Description

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2. The synchronizer according to claim 1, wherein the digital phase equalizer is made in the form of serially connected first, flip-flop, fourth NAND element. the fifth element of the NAND and the second trigger, and the third trigger connected in series, the sixth element of the NAND and the seventh element of the NAND, whose output is connected to another input of the second trigger, and the inverse output of the first trigger through the eighth AND element - is NOT connected to another input of the fifth NAND element, and the inverse output of the third trigger is connected via the ninth NAND element to the other input of the seventh AND-NO element, 13, the second input of the luecToro AND-NE element and the third trigger of the third trigger are combined and are the first digital input The phase phases, the second input of the fourth IS-NE and the first input of the first trigger are combined and are the second input of the 11 1-phase phase resolver, and the second inputs of the ninth AND-NOT element, the first trigger, the third trigger and the eighth AND-NO element are combined g are the third entrance of the U-1 paral; the phase reader, the inverse and direct outputs of the second trigger are respectively the first and second PDI inputs of the digital phase discriminator.

one

The invention relates to radio engineering and can be used to form a grid of frequencies in radio transmitting, radio receiving and radio measuring devices.

A digital frequency synthesizer is known, comprising connected in a colg1; o controlled oscillator, frequency divider with variable division factor, frequency-phase detector, first stable current generator and low-pass filter, as well as a reference oscillator and a second stable current generator connected between the output frequency -phase detector and low-pass filter input 1.

However, the synthesizer does not provide high speed when changing output frequencies.

The closest in technical terms to the present invention is a digital frequency synthesizer containing ring controlled oscillators, a variable division frequency divider, a frequency phase detector and a low pass filter, as well as a serially connected reference oscillator and a frequency divider with a fixed division factor 2

However, the speed of a known synthesizer when changing frequencies is insufficient due to the loss of time due to a significant overshoot caused by the principle of operation of the frequency-phase detector.

The purpose of the invention is to increase the speed when changing output frequencies,

The goal is achieved by including a frequency synthesizer containing ringed controlled oscillator, variable frequency division divider, frequency-phase detector and low pass filter, as well as a reference oscillator connected in series and a frequency division divider, me)) (the first output of the frequency divider with a fixed division factor and another input of the frequency-phase detector introduced serially connected digital

phase discriminator, first and second NAND elements, as well as the third NAND element, the first input of which is connected to the second output of the digital phase discriminator, the output of the third

element NAND is connected to another input of the second NAND element, the second input of the third NAND element and the second input of the digital phase discriminator are combined and connected to the second output

a frequency divider with a fixed division factor, the first output of which is also connected to another input of the first NAND element, and the output of a frequency divider with variable frequency (| k}). The division divider is also connected to the third input of the digital phase discriminator. In addition, 1frame1 phase discriminator is made in the form of serially connected first trigger, fourth IS-NOT element, fifth element, and second trigger, and the third trigger, sixth AND-NOT element and the seventh AND-NOT element in series, the output of which is connected in series to another input of the second trigger, with the inverse output of the first trigger through the eighth element AND-NOT connected to another input of the fifth element AND-NOT, and the inverse output of the third trigger through the ninth element AND-NOT connected to the other input of the seventh element AND - H Tue The first input of the sixth IS-NOT element and the first input of the third trigger are combined and are the first input of the digital faer discriminator. The second input of the fourth AND-NOT element and the first input of the first trigger are combined and are the second input of the digital phase discriminator. of the NAND element, the first trigger, the third trigger and the eighth NAND element are combined and are the third input of the digital phase discriminator, the inverse and direct outputs of the second trigger are the first and second outputs of the digital distinguish l phase. Figure 1 shows the structural electrical circuit of the proposed synthesizer, and Figure 2 shows the structural electrical circuit of the digital phase discriminator. The synthesizer contains a controlled oscillator 1, a divider 2 frequencies with a variable division factor (DPD), a frequency-phase detector (CFD) 3, a low-pass filter 4 (LPF), a reference oscillator 5, a divider 6 frequency with a fixed division factor (DFCD) , the first, second and third elements AND-NOT 7-9 and digital discriminator 10 phase. The digital phase discriminator contains the first trigger 11, the second trigger 12, the third trigger 13, the fourth, fifth, sixth, seventh, eighth And ninth elements AND NOT 14-19. 34 Synthesizer works as follows. In synchronism mode, short pulses on one FFD 3 input (from the DFCD 2 output) coincide with short reference pulses and to the other FFD 3 input, which arrive through the second AND-NE 8 element from the first DFCD 6 output through the first I-NE 7 element or with the second output DFCD 6 through the third element AND-NOT 9. The reference pulses from the first and second outputs DFCD 6 are equal in frequency, but differ in phase by 180. When switching the synthesizer from one frequency to another, the pulse period from the output of DPDD 2 differs from from the period of the reference pulses, for example, become Vits large, then in the FFD 3 a control pulse is formed, under the action of which the voltage on the memory capacity of the low-pass filter 4 begins to increase so as to eliminate the resulting mismatch, i.e. The period of the pulses from DPDC 2 begins at 1. The passage of the reference pulses to the second PFD 3 input with phase O or 180 is controlled by the digital discriminator 10 so that only those reference impulses whose phase is close to the phase of the pulses with DPKD 2 pass. Suppose first for PFD 3 the reference pulses with phase O are used, but when comparing the period of pulses from DPKD 2 with the period of reference pulses shifted on in the digital discriminator 10 through the fourth and fifth elements AND 14 and 15, the second reference pulse passes the input of the second trigger 12, since the first reference pulse with phase O sets first trigger 1 1 in the position allowing the passage of the subsequent reference pulse. As a result, the second trigger 12 is set to the position in which it is in the first. The output of the digital discriminator 10 appears zero potential, prohibiting the passage of reference pulses with a phase of 0 ° through the first element AND-HE 7, and at the second output a high potential allowing the passage of reference pulses with a phase 180 through the third element AND-HE 9. Akim thus, a phase change occurs; porosity pulses at the second input of PD 3, after which synchronization occurs without overshoot. In synchronism mode in the digital discriminator 10, one of the trigger 11 or 13, allowing the passage of reference pulses with phase O or 180, can be in random form, unlike the other trigger, which can produce a square-wave type pulse at the output. This is explained by the fact that, in phase matching mode, the compared sequences of pulses are close and there may be moments when there are two pulses of another sequence between two pulses of one sequence of skipping. This confirms the correctness of the selected phase of the reference signal. And for another trigger, the phases of the compared pulse sequences are shifted by 180, and therefore a meander is obtained at its output. At that, each time a negative impulse prohibits the passage of the second impulse through the corresponding element NAND 16 or 19. As a result, at the output of the 7th element NAND 17 there are no impulses that overrode the second trigger 12. Similarly, work occurs if the period of pulses from PDKD 2 when the error is less than the period of the reference pulses. Wherein . The digital discriminator 10 automatically determines with which phase of the reference pulses it is necessary to compare the FFD 3 pulses with the DPKD 2. In addition to the O and 180 phases, other phases can be compared, for example, with a small mismatch, the closer phases of the reference pulses can be used. Thus, the proposed digital frequency synthesizer has a higher response time when changing output frequencies, due to the fact that the phases and frequencies of the reference pulses are shifted by 180 ° and the pulses with DCDB are close, therefore the overshoot characteristic of the well-known synthesizer is significantly reduced or completely eliminated .

Claims (2)

1. A DIGITAL FREQUENCY SYNTHESIZER containing a controlled oscillator connected in a ring, a frequency divider with a variable division coefficient, a frequency-phase detector and a low-pass filter, as well as a series-connected reference generator and a frequency divider with a fixed division coefficient, characterized in that, with In order to improve performance when changing the output frequencies, between the first output of the frequency divider with a fixed division coefficient and the other input of the frequency-phase detector are connected in series digital phase discriminator, the first and second AND-NOT elements, as well as the third AND-HE element, the first input of which is connected to the second output of the digital phase discriminator, the output of the third AND-NOT element connected to another input of the second AND-NOT element, the second the input of the third AND-NOT element and the second input of the digital phase discriminator are combined and connected to the second output of the frequency divider with a fixed division ratio, the first output of which is also connected to the other input of the first AND-NOT element, and the output of the frequency divider with a variable coefficient ientom division is also connected to the third input digital distinguishing property. 1J9913 Figure 1 1 109913 2. The synchronizer according to claim 1, comprising the fact that the digital phase discriminator is made in the form of series-connected first, trigger, fourth AND-NOT element. the fifth AND gate element and the second trigger, and the third trigger connected in series, the six AND gate element and the seventh AND gate element, the output of which is connected to another input of the second trigger, the inverse output of the first trigger through the eighth AND gate NOT connected to another input of the fifth AND-NOT element, and the inverse output of the third trigger through the ninth AND-NOT element is connected to another input of the seventh AND-NOT element, the second input of the sixth AND-NOT element and the first input of the third trigger are combined and are the first digital difference input phase, the second input of the fourth AND-NOT element and the first input of the first trigger are combined and are the second input of the digital phase discriminator, and the second inputs of the ninth AND-element, the first trigger, the third trigger and the eighth AND-NOT element are combined and are the third digital input When the phase inverter, the inverse and direct outputs of the second trigger are the first and second outputs of the digital phase discriminator, respectively.