SU768000A1 - Device for receiving frequency manipulated signals - Google Patents

Description

(54) DEVICE FOR ACCEPTANCE OF FREQUENCY-MANIPULATED SIGNALS

one

The invention relates to telecommunications and can be used to receive continuous signals modulated with discrete frequency information.

A device for receiving frequency-manipulated signals, comprising a clock pulse generator, two phase locked loops and a phase detector 1, is known.

However, the known device has a lack of reliability of the received signals.

The purpose of the invention is to increase the reliability of received signals.

For this, a device for receiving frequency-manipulated signals comprising a clock pulse generator. Two nodes of phase-locked loop and phase detector, input edge selector, codefrequency converter, OR element and series-connected edge selector of the detected signal, standby multivibrator and digital integrator, whose outputs are connected to code-frequency converter inputs, auxiliary input and output are connected according to

output of the clock generator and the first input of the OR element, to the second input of which is connected the output of the clock generator, which is connected to the clock input of the digital integrator, to the additional inputs of which are connected the outputs of the second phase-locked loop node, the inputs of which are connected respectively to the outputs of the first node frequency control and an OR element whose output is connected to

10 to the first input of the first node of the phase locked loop, the second input of which is connected to the output of the input edge selector, while the output of the first node of the phase locked loop is connected to the first input of the phase

 the detector, the second input of which is connected to the corresponding output of the second node phase locked loop.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - timing diagrams explaining the operation of the phase detector.

A device for receiving frequency-manipulated signals contains a selector 1 of the fronts of the input signal, two knots 2 and 3 phase-locked loops (PLLs). phase detector 4, highlighter

of fronts of the detected signal, waiting for multivibrator 6, digital intruder 7, converter 8 code - h of frequency, element OR 9 and generator of 10 clock pulses (Fig. 1).

The device works as follows.

The output selector 1 of the fronts of the input signal generates short pulses corresponding to the moments of crossing the zero frequency-manipulated input signal. These pulses arrive at the second input of the first PLL node 2. The first PLL node 2 and the second PLL node 3 are made on the same functional bhey And I consist of the main frequency divider 11, the first selector 12 of the leading edge, the RS flip-flop 13, element I 14, the divider 15, the second allocated 16 front of the front and the element OR 17.

Phase detector 4 consists of an inverter 18, two elements And 19 and RS-flip-flop 20 ,.

Digital integrator 7 consists of two elements AND 21, two averaging dividers 22 and a reversible counter 23.

V At the beginning, we consider the operation of the device for receiving frequency-manipulated signals in a static mode, when either the frequency “press fn or the frequency” release foT comes to its input. moreover, the frequencies of the received signal and generator 10 clock pulses are nominal. In this case, there are no pulses at the output of the allocator of 5 edges of the detected signal, the waiting multivibrator

6 is in the initial state (at its output potential is “zero”), therefore, the pulses from the generator output 10 clock pulses to the inputs of the averaging dividers 22 are not

the state of the reversible counter 23 also arrives and does not change, and its Distinctive OU is equal to half its capacity. In this case, the average pulse frequency at the output of the converter In the code-frequency is equal to half the maximum frequency. The duration and time of: Tb Eugene These pulses are such that they do not accumulate in time with pulses at the output of the generator 10 clocks, so the output of the element OR 9 is average ClockTbt-tracking of pulses from the outputs. 10 clock pulse generator and 8 code-frequency converter.

For nominal terms, this frequency will also be nominal.

The division factors of the main division of bodies II and of the divider 15 of adding nodes

PLLs 2 and 3 are selected such that when the battery is switched on, the pulse inputs with nominal

following the frequency of the following, and the inputs

SRS flip-flops 13 pulses with double

the average frequency of the frequency-manipulated signal 2fo fn + W (due to frequency doubling in the selector 1 of the fronts of the input signal) at the output of the RS-flip-flops 13 will form a sequence of rectangular pulses with a duty cycle equal to

two (meander). This indicates a delay of pulses coming from the output of the selector 12 leading edges to the inputs of the RRS-flip-flops 13 Regarding the pulses arriving at their inputs S for a time tso equal to half the follow-up period of these pulses, i.e.

tso 0.5Go 0.5 (fH + foT)

For PLL nodes 2 and 3 to operate, it is necessary to ensure that the pulses at the inputs of the OR elements 17 do not coincide. When the frequency of the pulses at the inputs of the SRS flip-flops 13 changes, within the holding band of the PLL nodes 2 and 3, the time t 3 will change due to

0 which will change the duty cycle of the pulses at the output of the RS-flip-flops 13. The detection of the frequency-manipulated signal is based on this device. The first node of the PLL 2 is designed to reduce the influence of interference on the location of the edges of the received signal, and the second node of the PLL 3, together with the phase detector 4, detects an input signal, the principle of which is illustrated in FIG. 2. If the device to receive

0 frequency-manipulated signals enter the frequency fo 0.5 (fn + foi), then short pulses from the output of the selector 12 of the leading edges of the first PLL node 2 will follow at a frequency of 2fo and arrive at the input of the SRS flip-flop 13 of the second PLL node

i 3 and to the first input of the phase detector 4, i.e., to the inputs of the elements And 19. The division ratio of both main dividers 11 must be a multiple of two, then at its output the square-wave pulses will be

Q be in the form of a meander (Fig. 2a). At a signal frequency fc fo, the falling edges of these pulses will coincide in time with the pulses coming from the output of the first PLL node 2. If the frequency of the signal fc is less than fo (for example, fc foi), then

 tj 1zo, as a result of which short pulses from the output of the first node of the PLL 2 will coincide in time with the level of "zero at the output of the main divider 11 of the second node of the PLL 3, which is its output

p (Fig. 26). Then, the output of the inverter 18, which is part of the phase detector 4, will be level one and short pulses from the output of the first PLL node 2 will be fed through one of the elements AND 19 to the input of the RRS trigger 20 at the output of which is phase output detector 4, will be the level of "zero.

If the frequency of the fc signal is greater than fo (for example, fc fn), then the time

As a result, short pulses of the output of the first node of the PLL 2 will coincide in time with the level of the unit at the output of the main divider 1I of the second node of the PLL 3 (Fig. 2c). Then, the output of the inverter 18 will be the level “zero h short pulses from the output of the first node of the PLL 2 will poke through another element And 19 to the input of the SRS trigger 20, the output of which will be the level“ unit.

Thus, at the output of the device there will be a logical "one or logical" zero depending on whether the frequency of the received signal is greater or less than the average frequency.

The high noise immunity of the device of frequency-manipulated signals is provided by the filtering action of the PLL nodes 2 and 3.

A device for receiving frequency-manipulated signals insensitive to the instability of the characteristics of the input signal frequency and 10-clock pulse generator frequency by introducing into it a feedback circuit covering both PLL nodes 2 and 3, formed by the selector 5 of the detected signal, the waiting multivibrator 6, a digital integrator 7 and code-frequency converter 8.

At the beginning, suppose that the manipulating signal represents a deterministic sequence of "ones and" zeros ("points). The pulse duration T at the output of the waiting multivibrator 6 should be much shorter than the duration of the manipulating parcels. The units will be within 99% of the time, i.e., almost all the time, the potential of the unit will be supplied to the second input of the digital integrator 7.

Since the main and inverted outputs of the RS flip-flop 13 of the second PLL node 3 are connected to the third and fourth inputs of the digital integrator 7, the number of pulses arriving at the inputs of averaging dividers 22 from the generator output 10 clock pulses through AND 21 elements will depend on the RS flip-flop states 13. If the frequencies of the received signal fn and foT are nominal, then the time of receiving two different signs of different characters is the number of pulses arriving at the inputs of the averaging dividers 22 from the generator output 10 clock pulses It will be the same, since the change in time t.j for RS-flip-flops 13 relative to the value of tjp will be the same when receiving frequencies frt and foT. The division factor of the averaging dividers 22 is chosen such that, during the TO time, no more than one pulse appears at their output. Since the output of one separator 22 of the divider 22 is connected to the summing input of the reversible counter 23, and the output of the other one is subtracted from its 5 K) input, during reception of two parcels of a different sign, the state of the reverse counter 23 does not change. Since the outputs of the bits of the reversible counter 23, which are the outputs of the digital integrator 7, are connected to the inputs 8 of the 10 10 code-frequency converter, with a constant state of the reversible counter 23 the average pulse frequency at the output of this converter 8 will also not change.

If the frequencies of "pressing and" unwinding the received signal deviate from their nominal values, then the change in time t-j for RS-flip-flops 13 relative to the value tjQ will be different when receiving frequencies t and for

As a result, during reception of several 0 pairs of parcels of different characters, the number of pulses at the outputs of the averaging dividers 22 will be different, the state of the reversible counter 23 will change, which will result in a change in the average pulse frequency at the output of the code-frequency converter 8 and at the element output OR 9 ..

Since the boundaries of the holding band of the PLL nodes 2 and 3 depend on the frequency of the pulses arriving at their inputs, as a result of a change in the frequency of the pulses at the output of the OR 9 element, these boundaries will shift so that the average frequency of the received signal will coincide with the middle retention bands. Similar processes will occur when the frequency of the pulses at the generator output of 10 clock pulses deviates from the nominal value.

The circuit, which distinguishes 5 leading edges of the detected signal and the waiting multivibrator 6, is intended for normal functioning of the device of frequency-manipulated signals when receiving a random sequence of manipulating parcels and in static mode, when a long time-frequency or frequency or for frequency the circuit alternately connects to the input of averaging dividers 22 generator outputs 10 clock pulses by taking into account the RS flip-flop 13 state of the second PLL node 3 Receiving Gn frequencies and for, thereby allowing pairing of manipulating parcels

various marks used for digital integrator 7.

In the second case, as already noted, no adjustment of the frequency at the output of the element OR 9 will occur.

Claims (1)

Invention Formula A device for receiving frequency-manipulated signals, containing a clock pulse generator, two phase-locked loops and a phase detector, characterized in that, in order to increase the reliability of received signals, an edge selector for the input signal was inserted into it, a code-frequency generator, the OR element and the front edge detector of the detected signal connected in series, the waiting multivibrator and the digital integrator, the outputs of which are connected to the inputs of the code-frequency amplifier, are additional the stroke and output of which are connected respectively to the output of the clock generator and the first input of the OR element, to the second input of which the output of the clock generator is connected. pulses that is connected to clock input of a digital integrator, to the additional inputs of which are connected the outputs of the second phase-locked loop node, whose inputs are connected respectively to the outputs of the first phase locked loop node and the OR element, whose output is connected to the first input of the first phase-locked loop node, the second input of which is connected to the output the front edge selector, the output of the first phase locked loop node is connected to the first input of the phase detector, the second input of which This is connected to the corresponding output of the second phase locked loop node. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 227404, cl. H 04 B 1/30, 1966 (prototype).