SU1270775A1 - Control device for fast fourier transform processor - Google Patents

Abstract

The invention relates to the field of automatics and augmentation techniques and can be used to solve problems of spectral correlation processing of sequences of real and complex samples. The aim of the invention is to extend the functionality by calculating the Fourier transform of real and complex sequences. The device contains an AND node, an iteration register, a counter, two triggers, a synchronization node, an inverse code generation node, four AND elements, a block node, two subtractors, two ring shift registers, and a switch. This set of features makes it possible to achieve the goal of the invention. (L 2 Il.

Description

The invention relates to automation and computer engineering and can be used to solve the problems of spectral-correlation processing of sequences of real and complex samples.

The aim of the invention is to expand the functionality by determining the Fourier transform of real and complex sequences.

In FIG. 1 shows a functional diagram of the proposed control device for a fast Fourier transform processor (FFT). for action. binary code converted by subtractors 10 and 11 and ring shift registers 12 and 13 into the address code of accessing the blocks of the RAM of the processor.

• At the first and fifth outputs of the device, address codes are generated, and at the third and sixth outputs - write control signals - by reading operands for the processor's RAM blocks. At the second output of the device, codes of addresses of exponential coefficients W are generated, which are read from the processor constant memory block 15.

real and complex data arrays, in FIG. 2 is a diagram of a lock assembly.

The device (Fig. 1) contains a node of elements AND 1, a register of 2 iterations, 20 counter 3, triggers 4 and 5, a synchronization unit 6, an inverse code generation unit 7, an AND 8 element, a blocking unit 9, subtractors 10 and 11, ring registers 12. and 13 of the shift, switch 25, 14. elements And 15-17, switches 18-20.

Locking unit 9 (Fig. 2) contains AND elements - NOT 21 and 22, AND 23-28 elements, adders 29-31 modulo 30 li / two, HE 32 element, OR 33 element, trigger 34, OR element - NOT 35.

The device operates as follows.

In the case of processing valid sequences, input 0 receives a signal 0, opening elements 8 and 16 and closing element 16. At the output of element 15, a logical potential 0 is established, which blocks element 17 and controls the switches 18-20 so that the signals from the first inputs appear at their outputs. The switch 14, 45 is installed in the same state

At the direct outputs of triggers 4 and 5, potential 0 is set, and at the outputs of the bits of the counter 3 and register 2 iterations, potential 0 is also set. The outputs of trigger 4 are the outputs 53 of the device and determine the mode of operation> for the blocks of the RAM (0 - read, ' '1 - record).

A series of clock pulses from the first output of the synchronization unit 6 is supplied to the counting input of the trigger 5 and generates the initial output of the bits of the counter 3 and the direct output of the trigger 5

In the case of processing one complex sequence of data, input 1 of the processor receives signal 1, which blocks the elements And 8 and 16 and opens the element And 15.

The first n + 1 iterations of FFT computations occur similarly to the case of processing 4 real arrays. In this case, the synchronization unit 6 generates a series of pulses arriving at the clock input of the trigger 5, at the output of which, as well as at the outputs of the bit counter, the source code of the address of access to the processor RAM blocks is generated. This address word through the inverse code generation unit 7 is supplied to the inputs of the And element 16 of the subtractors 10 and 11, is converted by control signals from the direct and inverse outputs of the trigger 4, and is entered into the shift shift registers 12 and 13, the operation mode of which is controlled by the locking unit 9. The signals from the outputs of the discharges of the circular register 12. shift and through the switch 19 of the circular register 13 shift enter the address inputs of the blocks of RAM of the processor and specify the order of recording and reading of the operands. A sign of the transition to the calculation of the subsequent FFT iteration is the overflow signal of counter 3, which is fed to the clock input of the (n + 1) -bit register of 2 iterations, 'by which 1 is written to the upper bit of the register of 2 iterations when the stored information is shifted to the lower bits. The signals from the outputs of the bits of the register of 2 iterations either block or allow the passage of the source code from the outputs of the bits of the counter 3 through the element node And 1 to the address input of the constant bls

1271 processor memory. At the end of the (n + + 1) th iteration, the overflow signal of counter 3 into the least significant bit of the iteration register 2 records 1 from the second bit of the register. This logical 5 potential through the And element 15 enters the control inputs of the switches 18-20, the control input of the switch 14 puts them in a state in which signals from the second inputs pass to the outputs of the switch 1C. In addition, the element And 17 opens and passes to the input of the least significant bit of the address of the processor random access memory block a signal from the output of trigger-15 of gene 4, and trigger 5 generates control signals (write-read) of the processor random access memory blocks through block 9 (it is forbidden write to the blocks of one- 20 memory. Thus, the last (n + 2) -th iteration of the FFT is performed.

Claims (1)

The invention relates to automation and computer technology and can be used to solve problems of spectral correlation processing of sequences of real and complex samples. The aim of the invention is to extend the functionality by defining the Fourier transform of real and complex sequences. FIG. Figure 1 shows the functional scheme of the proposed control unit for the Fast Fourier Transform Processor (FFT) for valid and complex data arrays, Fig 2, a block node diagram. Device (| 1) ig. 1) hold the node elements And 1, register 2 iterations, counter 3, trigger1 4 and 5, node 6 synchronization, node 7 of the formation of the inverse code, element And 8, node 9-lock, subtractors 10 and 11, ring reg. 12 and 13 shift, switch 14. elements AND 15-17, switches 18-20 .. Interlock node 9 (FIG. 2) contains AND-NE elements 21 and 22, AND elements, adders 29-31 modulo two, NOT element 32, element OR 33, trigger 34, element YPI-NO 35. The device operates as follows. In the case of processing the actual sequences at the input And 1 post, the signal O, the opening element And 8 and 16 and the closing element And 16 On. In the output of the element 15, a logical potential is set, which blocks the element i-i 17 and controls which: yattopamil 18-20 so that at their outputs there is a signal from the first inputs. The switch 14 is set to the same state, the potential O of the triggers 4 and 5 is set to O, and the output to the bits of the counter 3 and the register of 2 iterations is set to the potential of the trigger of the trigger 4 The device outputs and determine the mode: 1) for RAM blocks of the processor (O - read, 1 - write Serial clock pulses from the first output node. 6 of synchronization received at the counting input of the trigger 5 tons; counter 3 on the direct output of the trigger 5 msec binary code converted by subtractors 10 and 11 and the circular shift registers 12 and 13 in the address code for accessing the processor’s RAM blocks.The address codes are generated on the first and fifth outputs of the device, and the read-write control signals for the memory blocks on the third and sixth outputs processor. At the second output of the device, codes of addresses of exponential coefficients W are read out from the processor's permanent storage unit. In the case of processing one complex sequence of data, the signal 1 enters the input of AND 1 of the processor, KOTOpbDi blocks the elements of AND 8 and 16 and opens the elements of AND 15. The first n + 1 iterations of the calculation of 1 and the FFT occur as in the case of processing 4 real arrays. In this case, the synchronization node 6 generates a series of pulses arriving at the clock input of the trigger 5, at the output of which, as well as at the outputs of the bit counter, the source code of the address of the processor to the memory blocks of the processor is formed. This address word through the node 7 of the formation of the inverse code is fed to the inputs of the element And 16 of the subtractors 10 and 115 is converted by control signals from the direct and inverse outputs of the trigger 4 and entered into the ring registers 12 and 13 shift. node 9 lock. The signals from the outputs of the bits in the ring register 12 shift and through the switch 19 ring ring register 13 shift arrive at the address 1 inputs of the processor's RAM blocks and set the order of recording and reading of operands. A sign of the transition to the calculation of the subsequent iteration of the FFT is the overflow of counter 3, arriving at the input of the (n + 1) -bit register of 2 iterations, which takes place; 1 record 1 into the highest register of the register of 2 iterations when the stored information is shifted towards the younger bits The signals from the inputs of the bits of the register of 2 iterations either block or allow the passing of the initial code from the codes of bits of the counter 3 through the AND 1 node of elements to the address input of the processor's permanent memory unit. At the end of the (n + +1) -th iteration of the overflow signal of counter 3, 1 of the second register bit is written to the low order of the register of iterations 2. This logical potential through the element 15 enters the control inputs of the switches 18-20, the control input of the switch 14 puts them in a state where signals from the second inputs pass to the outputs of the switches. And the element 17 also opens and passes to the input of the lower bit of the address of the RAM block of the processor a signal from the output of trigger 4, and trigger 5 generates control signals (write-read) of the RAM blocks of the processor through the blocking node 9 (this prohibits writing to one Thus, the latter is carried out, (n + 2) - FFT qi ite. Formula of Invention A control device for a fast Fourier transform processor containing a synchronization node, first and second triggers, a counter, an iteration register, a node of elements And, a node forming the inverse code, the first element I, the first and second subtractors, the first and second ring shift registers and the blocking node, the first output of the synchronization node being connected to the counting input of the first trigger, the forward output of which is connected to the counting input at the second trigger, the parallel output of the counter is connected to the first information input of the node And elements and the information input of the inverse code generation node, the overflow output of the counter is connected to the shift control input pe of the iteration node, the parallel output of which is connected to the second information input of the element node, output the first bit of the iteration register is connected to the control input of the node of the elements AI and to the first input of the element I, the output of which is connected to the control input of the node forming the inverse code, the output of which is connected to the summing inputs of the first and second subtractors, the outputs of which are bitwise connected to the information inputs of bits from the second to the (n + 1) -th, respectively, first and second ring shift registers, the outputs of the first and second ring shift registers and the output of the node elements Both are the first, second, and third outputs of the device, respectively, where the blocking node contains an OR-NOT element, an OR element, an NOT element, the first, second and third modulo-two adders, the first and second AND-NOT elements, the first, second swarm, third, fourth, five and sixth elements AND and a trigger; moreover, the input of the element is NOT connected to the first outputs of the first modulo-two adder and the OR element, the fifth input of the OR element is NOT connected to the counting input of the trigger, the output of the element is NOT connected to the first inputs of the first and second elements NAND and the first inputs of the first and second elements AND, the output of the element OR — NOT connected to the second input of the element OR whose output is connected to the first inputs of the third and fourth elements AND, the output of the third element AND connected to the second entrance first element And the direct input of the fifth element And, the output of the fourth element And connected to the second input of the second element And to the direct input of the sixth element And, the inverse inputs of the fifth and sixth elements And connected to the output of the first modulo two, right my and inverse outputs of the trigger are connected to the second inputs of the first and second elements of the NAND, respectively, whose inputs are connected to the first inputs of the second and third modulators, respectively, two, the second inputs of which are connected to the outputs of the second and first, respectively And, the outputs of the second and third modulators two locking nodes are connected to the shift control inputs of the second and first ring shift registers, respectively, the outputs of the fifth and sixth elements of the lock node are the fourth and fifth device outputs, output () The second bit of the register of iterations is connected to the second input of the first modulo-two interlock unit, the input of the element ILINE of which is connected to the parallel output of the counter, and the output of the first bit of the register of iterations is connected to the input element of the blocking node NOT, 1 characterized by the fact that, in order to extend the functionality by determining the Fourier transform of real and complex sequences, the second, third and fourth elements of the And, first, second, third and fourth switches are introduced into it, the third input of the first element And is connected to the first input of the second element And and the inverse input of the third element And is the input setting the device mode, the second input of the second element And is connected to the input of the third element And and n connected to the output of the first bit of the iteration register, the output of the second element I is connected to the second input of the fourth element I and to the control inputs of the first, second, third and fourth switches, the first input of the fourth element I is connected to the first information input of the first and third switches and connected to the direct output of the second trigger, the inverse output of which is connected to the first information input 56 of the second switch, the second information input of which is connected to the inverse output of the first trigger, forward whose input is connected to the second information inputs of the first and third switches, the outputs of the first and second switches are connected to the second inputs of the third and fourth elements AND of the blocking node, respectively, and the subtractive inputs of the first and second devices of the device, respectively, the sixth and seventh outputs of the device, output The third switch is connected to the first input of the first element And the output of the first bits of the first and second circular shift registers, the output of the third element And p dklyuchen to the inverted input node of the AND, the output register of the second ring is connected to the information input of the fourth switch whose output is the output of the eighth, and the output of the fourth AND gate connected to the output node elements I. fug /