SU1764058A1 - Device for vector processing - Google Patents

Description

one

(21) 4872539/24

(22) 07.19.90

(46) 09/23/92. Bul No. 35

(71) Moscow Institute of Radio Engineering, Electronics and Automation

(72) N.N.Evtikhiev, E.V.Emelin, D.E.Krasnov, I.V.Lanin, E.G.Litvinov and V.L. Taubkin

(56) USSR Copyright Certificate No. 1256041, cl. G 06 F 15/20,1985.

European patent N 0049039, CL. G 06 F 15/347, published. 1984

(54) DEVICE FOR PROCESSING VECTORS

(57) The invention relates to computing and can be used as a specialized calculator in data processing systems. The purpose of the invention is to increase the speed when performing operations

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Y (f (ai, bi) l 3i bi, as well as the extension

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functionality due to

function number (ai bi). Device co i i o

holds two input registers 1, 2, four buffer registers 6, 7, 10, 11, three multiplexers 4, 5, 12, arithmetic logic unit 3, multiplier 9, unit 8, adder 13, result register 14, shift register 15 and a function selection register 16. Achieving the goal is ensured by a new structure of the device, which makes it possible to organize pipeline processing of the elements of vectors 1, sludge.

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The invention relates to computing and can be used as a specialized computer in data processing systems.

A device is known that contains a matrix of cells, each of which has AND, OR, NOT, triggers, and is designed to perform a vector compression operation. A disadvantage of the known device is the narrow functionality that does not allow to perform

operations T (f (a, bi)) 2, 2E | D | and

i 0

i 0

2.J (ai. Bi), where ai and bi are the corresponding

i 0

elements of the first and second vectors having dimension N; f (a ,, bi) is an arbitrary simplest function of two arguments; Si is a binary correlation function of two vectors.

Closest to the invention is a device for processing discharged vectors containing nine buffer registers, an arithmetic logic node, a control logic node, a shift register, and a counter. The disadvantage of this device is its low speed.

The purpose of the invention is to increase the speed when performing on vectors

operations of type 2) (f (a ,, b,)), 2a b | - a

also extending the functionality by calculating the function

(a ,, b,).

i 0

The goal is achieved in that the vector processing device contains the first and second input registers, the function selection register, the arithmetic logic unit, four buffer registers, the result register and the shift register, the first and second outputs of which are connected respectively to the control inputs of the first , the second, third and fourth buffer registers, and the inputs of the first and second operands of the device are connected respectively to the information inputs of the first and second input registers, the outputs of which are connected The inputs of the operation code of the device are connected to the input of the function selection register, the output of the result register is connected to the output of the device, the first synchronization input of which is connected to the synchronization input of the first input register, and the start input of the shift register and the synchronization input of the second input register is connected to the second synchronization input of the device,

the control input of the result register is connected to the third input of the shift register; three multiplexers, a unit adder, a multiplier and an adder are entered, the result register information input

connected to the output of the adder, the inputs of the lower bits of the first term of which is connected to the output of the first multiplexer, the first and second information inputs of which are connected respectively to the output of the significant bits of the third and the output of the fourth buffer registers, the information input of the third buffer register is connected to the output of the multiplier, the first and The second information inputs of which are connected respectively to the outputs of the first and second buffer registers, the information inputs of which are connected respectively to exits

second and third multiplexers, the first information inputs of which are connected respectively to the outputs of the first and second input registers, the first output of the function selection register is connected to the input of the arithmetic logic node operation mode, the output of which is connected to the second information inputs of the second and third multiplexers and the adder input whose output is connected to the information input of the fourth buffer register, the control inputs of the second and third multiplexers are connected to the second output p The function selection register, the third output of which is connected to the control input of the first multiplexer, the output of the result register is connected to the input of the second term of the adder, the inputs of the high-order bits of the first term of which are connected to the output of the sign bit of the third buffer register.

Functional diagram of the device shown in the drawing.

The device contains the first 1 and second

2 input registers, arithmetic logic unit 3, multiplexers 4 and 5, buffer registers 6 and 7, adder of units 8, multiplier 9, buffer registers 10 and 11, multiplexer 12, adder 13, result register 14, shift register 15, selection register functions 16, informational inputs 17 and 18, function setting input 19, output 20, device synchronization inputs 21 and 22.

The device works as follows. Before starting work, the registers 1,2,6, 7, 10, 11, 14, 16 are reset and the register 15 is reset to the initial state (the reset and initial settings circuits are not shown in the drawing). Then, at the input 19 into the register 16, a control word is entered, through which the elementary function implemented by node 3 and the multiplexers 4, 5 and 12 are set (the synchronization circuits are not shown in the drawing). The device then performs the actual processing as follows.

The vectors A and B are fed to the input of the device element by element, but asynchronously. The element of vector A is fed through input 17 to register 1 and is accompanied by a gate pulse from input 21 to write to the register. The corresponding element of vector B is fed through input 18 to register 2 and is accompanied by a strobe from input 22 for writing to the register. The write gate from input 22 is also input to the shift register 15, which performs the function of the time delay of the gate. The pulses shifted from the register 15 are shifted in time with respect to the strobe from the input 22 to the inputs of the buffer registers 6. 7, 10, 11 and result register 14. By switching the multiplexers 4, 5, 12, three modes of operation of the device are established.

In the first mode, after writing the corresponding elements of the vectors A and B to registers 1 and 2, the function is performed in block 3 and the result of the operation, passed through multiplexers 4 and 5, is recorded in registers 6 and 7 by a gate from register 15. The contents of registers 6 and 7 are multiplied by the multiplier 9 and is written to the buffer register 11 by the gate with the shift register 15. The contents of the register 11 through the multiplexer 12 enters the adder 13 and the result of the operation is written to the result register 14. Thus, the first specified function of the device is realized . In the second mode, after writing to registers 1 and 2 of the corresponding elements of vectors A and B, information is multiplied through registers 6 and 7 into registers 6 and 7. Next, the calculation order is the same as in the first case. This is how the second device function is implemented. In the third mode, after writing the corresponding elements of the vectors A and B to registers 1 and 2, the prescribed function is performed in block 3 and the result of the operation is fed to the input of the adder of units 8, the information from the output of which is recorded in the buffer register 10 by strobe from register 15. The output of register 10 through multiplexer 12, is applied to the input of adder 13 and is recorded in register 14 by the gate from register 15.

This mode implements a third device operation function.

Vectors A and B are fed to the input of the device sequentially, and the output of register 14 is the result of the selected vector processing function.

The invention allows to increase the speed of the device when performing

operations type 2) OCh3 - bi)) 2 2l a, b,,

which is achieved mainly through the use of pipelining of vector elements and expanding the functionality

the device’s capabilities due to the implementation of the function ЈЛ (ai, bi), where a and b, i 0

corresponding elements of the first and second vectors having a width N;

f (ah bi) is an arbitrary simplest function of two arguments; 2 / i is the binary correlation function of two vectors.

Claims (1)

Apparatus of the Invention containing the first and second input registers, the function selection register, the arithmetic logic unit, four buffer registers, the result register and the shift register, the first and second outputs of which connected respectively to the control inputs of the first, second, third, and fourth buffer registers, with the inputs of the first and second operands of the device connected respectively to the information inputs of the first and second input registers, the outputs of which are connected respectively to the inputs of the first and second operands of the arithmetic logic node, the input device operation code is connected to the input of the function selection register, the output of the result register is connected to the output of the result of the device, the first synchronization input of which is connected to the synchronization input of the first input register triggering the shift register and the synchronization input of the second input register are connected to the second synchronization input of the device, the control input of the result register is connected to the third output of the shift register, characterized in that, in order to increase speed when performing P over vectors of operations of type Ј ((a - bi)), i 0 P 2a i bi, as well as extensions to functional 0 capabilities by calculating the func ktsiy .if (ai bi) (where ai and bi are the corresponding i 0 the elements of the first and second vectors having the width N; f (ai, bi) is an arbitrary simplest function of two arguments; 2i is the binary correlation function of two vectors, three multiplexers, a unit adder, a multiplier and an adder are entered into it, the information input of the result register is connected to the output of the adder, the lower-order inputs of the first addend are connected to the output of the first multiplexer, the first and second information inputs which is connected respectively with the output of the significant bits of the third and the output of the fourth buffer registers, the information input of the third buffer register is connected to the output of the multiplier, the first and second The information inputs of which are respectively connected to the outputs of the first and second buffer registers whose information inputs are respectively connected to the outputs of the second and third multiplexers, the first information inputs of which are respectively connected to the outputs of the first and second input registers, the first output of the function selection register the operating mode of the arithmetic logic unit, the output of which is connected to the second information inputs of the second and third multiplexers and the sum input ora units, whose output is connected to a fourth data input buffer register control inputs of the second and third multiplexers are connected to the second output of the function select register, the third output of which is connected to the control input of the first multiplexer, the output of the result register is connected to the input of the second term of the adder, the inputs of the higher bits of the first term of which connected to the output of the sign bit of the third buffer register.