SU1619252A1 - Device for processing unclear information - Google Patents

Abstract

The invention relates to computing and technical cybernetics and can be used in special processors for processing fuzzy information, as well as in constructing technical tools for modeling reasoning and automating decisions in fuzzy conditions. The purpose of the invention is to expand the scope by enabling the calculation of the result of fuzzy logic operations with limited operations and reducing the number of information outputs of the device. The device contains two shift registers, three switches, a group of elements AND, an element AND, an element OR. The goal is achieved through the use of a unitary code and switches, providing the issuance of a direct a or inverse odd value of S variable. 1 ill., 1 tab. WITH/

Description

The invention relates to computer engineering and technical cybernetics and can be used in specialized processors for processing fuzzy information, as well as in constructing technical tools for modeling reasoning and automating decisions in fuzzy conditions.

The aim of the invention is to expand the class of tasks to be solved by computing functions of fuzzy logic with operations of implication, conjunction implication, disjunction, negation, Scheffer stroke, Pierce arrow.

The drawing shows the block diagram of the device.

The device consists of two shift-. output registers 1 and 2, switches 3,

and 4, a group of elements And 5, element And 6, element OR 7, switch 8, each of the switches 3,4 and 8 contains elements AND - OR 9, the device has inputs 10 of the first and 11 of the operands, clock input 12, input 13 start, inputs 14-16 settings, outputs 17 bits of the result.

Registers 1 and 2 are used to receive, shift and store unitary codes of numbers supplied from switches 3 and 4, respectively. Switches 3, 4 and 8 serve for direct or inverse transmission to their outputs of unitary codes, numbers supplied to information inputs. As a result of the inverse transmission, at the output of the switch, the negation of the number A applied to its information input is formed.

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The algorithm of the device is as follows.

The values of the variables A and B, applied to the information inputs of the first and second switches, respectively, are then transferred from the switches (depending on the type of operation) either without change, or in a transformed form (as a negative) to the first and second shift registers, respectively. After this, the contents of both registers are simultaneously shifted. In the first register, the content is shifted toward the higher bits, and in the second toward the younger bits. The signal of the end of the shift and the formation of a limited sum of the numbers recorded in the registers will be the presence of a unit either in the high order of the first register or in the low order of the second register. By the same signal, the contents of the first register are transmitted to the third switch, which, depending on the type of operation, either transmits the number from the first register in unchanged form to the device outputs, or forms a negative of the received number and transfers it to the output. Each i-th of three switches by yn

the equal signal yj 1, where, 3, transmits the number from the information input to the outputs unchanged, and

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lou y transmits to the outputs the negation of the number submitted to the information inputs.

Thus, a sign determining the receipt of the result of one or another of the logic

 operations on variables A and B ,, l

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there will be a set of control signal values (Y {, UZ. 9 y – j) at the control inputs of the three switches. The correspondence between the operation performed and the set of values of the control signals y ,,, D5 (, 2, ..., t, where t is the most significant bit

y, UZ is shown in the table.

The simplicity of the algorithm for performing these operations indicates the advantage of the unitary code over the binary code in this case.

The device works as follows.

At the inputs 10 and 11 of the switch QB 3. and 4, the unitary t-bit codes of the values of the variables, respectively, A and B, are given. By the signal from the device input 13, the values from the outputs of the switches 3 and 4 are written respectively to registers 1 and 2. To input 12

A device for processing fuzzy information containing the first and second shift registers, the group of elements AND and the element OR, and the outputs of the bits of the first shift register are connected to the first inputs of the corresponding elements AND of the group, characterized in that, in order to expand the class of tasks to be solved computing functions of fuzzy logic with the operations of implication, conjunction implication, disjunction, Schaeffer stroke negation, Pierce arrow, three switches and the I element are entered into it, and the inputs of the first and second operands of devices -keeping connected to data inputs respectively lane first- and second-switches whose outputs are connected to data inputs of the first and second-shift register, the output of the 1st discharge of the first shift register. sh

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input operands) is connected to the first input of the “-th element AND group, the output of which is connected to the first input of the 1st element AND group, the output of which is connected to the information input of the 1st bit of the third switch, the output of the m-th bit of the first shift register connected to the first input of the OR element, the second input of which is unified with the output of the first bit of the second shift register;

clock pulses come in through the AND 6 element to the shift control inputs of registers 1 and 2. The contents of register 1 are shifted towards the higher bits, and the contents of register 2 towards the lower bits until either the highest bits Register 1, or in the lower register 2 is not in accordance with the unit. As soon as this happens, a single signal appears at the output of element 7, which closes element 6 for passing clock pulses to the inputs of the register shift control and simultaneously opens elements of group 5 for transmitting the contents of register 1 to the information inputs of switch 8.

Claims (1)

Invention Formula (, 2, ..., t, where t is the oldest bit A device for processing fuzzy information containing the first and second shift registers, the group of elements AND and the element OR, the outputs of the bits of the first shift register are connected to the first inputs of the corresponding elements AND of the group, characterized in that, in order to expand the class of solved problems by calculating functions of fuzzy logic with the operations of implication, conjunction implication, disjunction, negation, Scheffer stroke, Pierce arrow, three switches and the element I are entered into it, and the inputs of the first and second operands of the device oystva connected to data inputs of the first and second switches, the outputs of which are connected to the data inputs of the first and second shift registers, the output of the 1st discharge of the first shift register. sh input operands) is connected to the first input of the “-th element AND group, the output of which is connected to the first input of the 1st element AND group, the output of which is connected to the information input of the 1st bit of the third switch, the output of the m-th bit of the first shift register connected to the first input of the OR element, the second input of which is connected to the output of the first bit of the second shift register, the output of the element OR is connected to the second inputs of the AND elements of the group and the inverse input of the AND element, the direct input of which is connected to the input of clock pulses device, the setup input of which is connected to the control inputs of the switches, the output of the element I is connected to the shift inputs of the first and second shift registers, the write resolution of which is connected to the start input of the device whose output is connected to the output of the third switch, the first shift register is shifted to the side older bits, with each switch containing a hectare of 2I-OR elements, the first direct input The first element 2I-OR is connected to the information input of the 1st switch bit, the second direct input of each element 2I-OR is connected to the control input of the switch, the third direct input of the 1st element 2I-OR is connected to. the information input of the (m-i + 1) -ro bit of the switch, the control input of which is connected to the inverse input of element 2I-OR, the outputs of the element 2ID- IDN are connected to the outputs of the corresponding bits of the switch. Operations R Formula 15 / 3