SU896691A1 - Device for determining error location in the line of matrix store - Google Patents

Description

(54) DEVICE FOR OPERATION OF LOCATION OF ERRORS IN THE LINE OF THE MATRIX DRIVE

one

The invention relates to memory devices and can be used for calculating and subsequently correcting errors in memory devices with two-dimensional organization of recorded information, in which information is recorded and read by arrays represented as rectangular blocks, in particular, the invention can be used in memory devices. on magnetic, pour with several tracks.

Devices are known for determining the location of errors in a row of a matrix accumulator, in particular in a row of a rectangular block of binary information.

One of the known devices contains the calculator of the line error vector and the calculator of the error line number, while the calculator of the line error vector consists of a modulo-two adder with m inputs and an n-bit shift register connected to the output of this adder (t xn is the size of the information block ), and the error row number calculator contains a shift register of m identical cells, each consisting of a modulo-two adder and a memory element, iT) indicators of the number of the erroneous line, executed by each of the modulo-two adders, trigger and auxiliary delay elements 1.

The main disadvantage of this device is lowered memory efficiency.

Of the known devices, the closest technical solution to the present invention is a device containing a computer for the error line vector calculator and a computer for the error line number connected to the device inputs, while the computer for the error vector line consists of a 3-modulo -input adder and the output of the dv (mn) -discharge shift register; the calculator of the error row number contains a converter of input signals; a ring shift register with feedback; indicators corresponding to The two registers mentioned above and when the number of indicators is less than gp is a pulse counter. shift, the converter of input signals consists of t-1 modulo-two adders with an average number of inputs close to, the ring shift register consists of t-1 cells made up of each adder modulo two, with two or three inputs, and a memory element, the first in of the adder of each cell connected to the corresponding output of the converter, the second - with the output of the previous cell, counting around the ring ,,. and the third inputs of certain modulo-two adders are connected to the output of the last register cell. {2 The main disadvantages of this device are the complexity of entering the calculator of the error row number and the large depth of the circuit of this calculator (a large number of elements in the signal path). ), which adversely affects the reliability and speed of the device. The purpose of the invention is to increase the reliability and speed of the device with a simple number of lines. The goal is achieved by the fact that in the device for determining the location of errors in the rows of the matrix accumulator, there are two modulo t-input adders (t is a simple number) whose inputs are the device inputs and the outputs are connected to the inputs (t-1) a separate shift register, the output of which is one of the device outputs, a ring shift register containing two-modulo two-input adders and memory elements, the outputs of which are connected to the inputs of the corresponding information indicators, the outputs of which are connected to counter inputs, the outputs of which are other output device is of a first input of each two-input adder modulo two are connected to the corresponding input device, the output - to the input of the memory element of the same name, and the second input - to the output pred1 1duschego memory element. In this case, the indicator of correspondence of information is advisable to perform in the form of an indicator of identity, i.e. a block containing a non-AND element and modulo-two adders, the outputs of which are connected to the inputs of the non-AND element, the output of which is the output of the information correspondence indicator, whose inputs are the inputs of modulo-two adders. FIG. Figure 1 shows a diagram of the proposed device with one identity indicator and calculator of the error row number (information block with dimensions m x (, 4); Fig. 2 shows the arrangement of information and check symbols and groups of symbols included in each check in this block. Device (Fig. 1) contains the calculator 1 of the line error vector and the calculator 2 of the number of the erroneous line.The calculator of I contains the G input adder 3 for the double (and (t − 1) -discharge shift register 4. The calculator 2 contains the circular shift register 5, indicator 6 matches and formations, made in the form of an identity indicator, and counter 7. Register 3 contains elements of 8 and four and two-input adders 9 modulo two. The first input of each adder Y is connected to the corresponding input of the device, the output to the input of the memory element 8 of the same name, and the second input to the output of the previous memory element 8. The indicator 6 contains adders 10 modulo two and a non-AND element 11 whose inputs are connected to the outputs of the adders 10, and the output is the output of the indicator 6 whose inputs are the inputs of the adders 10. The output of the register Country 5 with one of the inputs of the element NON 11 (the dash-dotted line in FIG. l) for the operation of the device is not essential, but may be useful in diagnosing malfunctions of the device. The counting input of the counter 7 is input 12, another counter input connected to the output of the element AND-11 is used to stop the counting. The outputs of the device are the output of the last register cell of the 4th shift, from which you find the vector of line errors and the outputs of counter 7, displaying the number of the error line.

The operation of the device is based on the fact that in the rectangular block being written to the rectangular block, one line and one column are reserved for the check characters, and these characters are selected when writing in a certain way. The location of the recorded characters in the block and their splitting into test groups for the case in question is shown in FIG. 2. The dashed lines denote the t-1 group of checks covering each symbol of one column (vertical checks). Dashed-dotted lines denote pack of checks covering each t-1 characters located in different rows and columns (skew checks). From the point of view of the record, it is convenient to use the last column for the check characters, which makes it possible to dispense with the buffer memory during recording. The check string can be any string, for example, the last (). The values of the check characters when writing are chosen so that the sum modulo the two total characters of any check group is zero. Moreover, in the absence of errors for any, 1,. .., t-2, i.e. For each vertical check, condition 5, and for each, 1 .. is fulfilled. ; gp-, i.e. for each skew check, the condition С с |. . .0 (here, the symbols are modulo two, and the indices are modulo m). Each character of any one line is included in one vertical and one skew check. Therefore, if some characters of a single line are read with an error, the checksums corresponding to these characters will be equal to one, and not zero.

The device works as follows.

When reading from a block of information on columns, beginning with the first (), let some or all of the characters of a single row with an unknown number i read with errors. When reading the j-th column, the j-th character of the vector i1 row error Jii S Back is entered into register 4 from the output of the adder 3, after reading the register 4 contains all the characters

966916

error vector of the i-th line E

 1.}. O .--.

In this case, the element I of the error vector is located in the j-top from the end of the cell. 5 In the ring register B of the shift for reading, sequential calculation of oblique checks is performed, as a result of which, upon completion of reading, the register also contains

10 vector of errors. If the register cells are numbered 5 with the same indices as the corresponding entries for the cells of the row,, 1, ..., t-1, the element 1. of the error vector will be contained in

15 cell with the index m-2 + i-j (addition modulo m). So, if errors occurred in the row with the index, the error vector elements of this row

about Oio4-, about respectively

Go in cells with indices t-2, t-3,... 1,0 (in our case in the third, second, first and zero cells). When connecting the inputs of the indicator 6 to the outputs of registers 4 and 5 (Fig. 1)

JS and with errors in the string, the presence. the identities of the two matched vectors are noted immediately upon completion of the reading, and the initial zero is fixed in counter 7

30 condition. If errors occurred in the row with i 0, then the identity signal at the output of indicator 6 after the end of reading is absent. In this case, the contents of register 5 shifts J5 from cell to cell until the appearance of the identity signal. The number of shifts B is counted by the counter 7, and the number of the erroneous line is determined from the readings of the counter 7 as

40 mod m. In this case, the errors in the rows 0,1,2,3,4 correspond to the readings of the counter O, 4,3,2,1. In the absence of errors, registers 4 and 5 upon completion of reading

j contain only zeros, indicator 6 indicates the commodity, and zero is recorded in the counter 7.

A device with one identity indicator (Fig. I) is the simplest and most reliable. Circuit depth

SO register 5 and indicator 6 is minimal, which provides speed when shifting and indicating the weight. However, to determine the error line number, after the end

Claims (2)

55 reads may require up to t-1 shifts. The maximum number of necessary shifts can be reduced down to zero by increasing the number of indicators 6. If we introduce m indicators 6 into the device, and connect the inputs of the i -th indicator to the outputs of register 5 in accordance with the location of the elements of the error vector -i -th lines, the error line number is determined immediately after the end of the reading by the identity signal at the output of the corresponding indicator. If there are two indicators, the maximum number of shifts is reduced to m - (/. Other intermediate cases are possible. If the number of indicators is less than vn, the number of the erroneous line is determined by the number of shifts required to indicate the identity by one of the indicators, and by the number of the indicator, In comparison with the known, the proposed device has the following advantages: The converter of input signals containing in the prototype T-1 adders with an average number of inputs close to rr / is excluded from the device. ij. In the ring register, all cells are made and connected in the same way, i.e., 1 matrices with three inputs and the corresponding feedbacks are known in them. At least one corresponding indicator (identities) is sufficient to determine the error in any of the m lines. while in the well-known error indicator, one more specific indicator is required to indicate the error. With the same number of indicators, two) the maximum number of shifts required for the indication (identity) in the proposed device is almost half as many in the famous. With any number of indicators in the device, they are all identical indicators of identity, whereas in the well-known all indicators are different, and except for the first two, they are more complex and less fast-acting than indicators of identity. Claim 1. A device for determining the location of errors in a row of a matrix accumulator containing a modulo two-way adder, two inputs (t prime), whose inputs are device inputs, and the outputs are connected to inputs of the (t-1) -discharge shift register, output which is one of the outputs of the device, a ring shift register containing two-input modulo-two adders and memory elements whose outputs are connected to the inputs of the information correspondence indicators whose outputs are connected to the inputs of a counter The outputs of which are other outputs of the device, characterized in that, in order to increase the reliability and speed of the device, in it the first input of each two-input modulo two adder is connected to the corresponding input of the device, the output to the input of the memory element of the same name, and the second input - to the output of the previous memory element. 2. The device according to claim 1, characterized in that the information compliance indicator contains a NOT-AND element and modulo-two adders, the outputs of which are connected to the inputs of the NOT-AND element, the output of which is the output of the information compliance indicator, whose inputs are inputs adders modulo two. Sources of information taken into account in the examination 1.IEEE Transactions on Computers. V. 25, No. 6, 1976, p. 642-645. 2.IBM Journal of Research and Development, v. 18, No. 6, 1974, p. 579-588 (prototype). yg, f 1 41 К l Ч1 41 Ч Ч 41 I I | I I I RCH I l | V h N h | 0ugh “1, |