SU1608637A1 - Data input device - Google Patents

Abstract

The invention relates to computing and is intended for use in information input devices primarily from a keyboard when creating machine carriers or data input to an ACS and a computer. The purpose of the invention is to increase the speed of the device. For this, a multiplier 4, a block of permanent memory 7, an address driver 11, a second delay element 13, a pulse generator 16, and a BAN 17 element are entered into the device. The formalized data to be entered is prepared taking into account specific operator errors by calculating the excess bits as some functions from the values of information symbols of individual details. The device computes the value of the control character according to the same rule. If the values entered by the operator and the characters calculated by the device are the same, the details are considered to be entered correctly and the operator enters the following details of the data. If the characters do not match, the device generates an error signal, and the operator repeats the set of incorrectly entered props. 1 il.

Description

The invention relates to computer technology and is intended for use in information input devices primarily from the keyboard when creating computer storage media or entering data into a computer and computer.

The aim of the invention is to improve the performance of the device.

The drawing shows a functional diagram of a device for inputting information,

The device comprises a keyboard 1, a register 2, a memory block 3, a multiplier 4, a comparison block 5, an adder 6, a permanent memory block 7, a counter 8, a first delay element 9, a first, an OR 10 element, an address shaper 11, a pulse shaper 12, the second delay element 13, the second element OR 14, the display unit 15, the pulse generator 16 and the element BAN 17.

Keyboard 1 is designed to issue code combinations of input characters to the input of register 2, Register 2 is designed to store code combinations of input characters. The capacity of the register is determined by the capacity of the code combinations received from the keyboard 1.

Block 3 RAM is designed to store code combinations of the information part of one attribute. The memory capacity is determined by the capacity of the code combination of one character and the length of the props.

The multiplier 4 by the control signal performs the function of multiplying two numbers, the code combinations of which are supplied to its inputs.

Block 5 comparison is intended for comparing the codes received at its inputs, and the signal arriving at its control input, gives signals of coincidence or mismatch of code combinations.

The accumulating adder 6 performs the function of summing over a given module of numbers.

Block 7 of permanent memory is designed to store the coefficients (weights) assigned to the corresponding positions of the controlled details.

Counter 8 has a conversion factor. that one. equal to the length of the controlled details.

The address generator 11 is intended for generating the addresses of the free field of the memory of block 3 and the addresses of the stored coefficients in block 7 and can be implemented by connecting the counter and the decoder in series with it.

The pulse shaper 12 is designed to issue control pulses when the state of its input changes.

The display unit 15 is intended to indicate an error sign in case of incorrect entry of the requisite by the operator.

The device operates as follows.

Suppose that the information prepared for input is a set of details of a given length I, and a control bit in the system of excessive details coding is formed as the remainder of dividing by a given module ξ the sum of the products of the values of information bits and the pre-assigned weights (coefficients) od, i.e. the procedure for calculating the control discharge is reduced to the form - Σ hell mod £

1 = 1

Such redundant coding systems are called simple weighted modular control systems (PMTCS).

In formalized digital details at £ = 10, to increase the detecting ability, sets of weights 10 (1), 10 (1, 3, 9, 7) or 10 (1, 9) are used. The length of one data attribute can be selected in the range of five to ten characters.

’Suppose a formalized document prepared for input consists of a set of details, the information part of each of which has a length of I = 8, and the control digit is calculated using the PCM system 10 (1, 3, 9, 7). Then the counter 8 of the device will give an overflow signal to its output when nine pulses arrive at its input, the following information will be written into the coefficient memory block: in the zero and fourth memory cells, the unit code, in the first and fifth - the triple code, in the second and sixth code the numbers nine, in the third and seventh - the code of the number seven.

In the initial state, register 2, adder 6, counter 3, address generator 11 are reset to zero, there is no information in the RAM block 3, the pulse generator 16 is turned off. Counter 8 has a conversion factor equal to the length of the information and control part of the attribute. In the read-only memory block, coefficients are written in accordance with the applied PCKM system for ξ = 10.

When collecting information, the code of the next character is received on the code buses to

1 input to the delay element 9. How the recording will take place ^{- the} information in page 2 and the code combination of the entered memory cells of the RAM unit 3 (driver 11 addresses the information inputs of register 2. With the ad code, the contents of the counter 8 increment in time and the clock pulse will receive the regs symbol to appear at its output, with the output of delay element 9 through the element PROHIBITION 17, a clock will arrive, which will record the code combination in zero; it will be in the zero state); it will allow the code combination of the received symbol to be multiplied by the explicit snoring coefficient, after the delay time of the delay element 13. the delay will record the resultant cut through the OR element 10, the sync pulse / clock will be input to the shaper 11 and the memory and block 7 of the permanent memory.

I, by singing a clock pulse from the keyboard, 1 character is recorded in register 2, but 10 in the zero cells of block 7 post-volt in the adder 6 modulo ξ. Od20 sresa and the reverse front will change the alternate field of block 3 operational

Code combinations arriving at block I of comparison 5 have an effect on his wound, since from the output of counterI to his input of the enable of comparison the inhibitory zero potential drops · by entering a control character, the record of his howl combination in register 2 is logged in 8 post;

al. The operation of the device in this mode continues until the infermation part of one attribute is entered. It is encoded as when entering information symbols, but the clock received at the input of counter 8 will ensure that a single potential appears on its output (overflow signal), which will allow a comparison of the code combination of the entered control symbol and the code combination calculated by the device and stored in adder 6, and will also provide a pulse output by the shaper of 12 pulses. The pulse from the output of the shaper 12 pulses will translate the shaper 11 addresses the passage of the clock from the output 'of the delay element 9 to the output of the element BANS 17.

to zero state and prohibit

If the code combinations, the progressive inputs of the comparison unit 5 match, the first output of the comparison unit 5 is then 55:

is the unit potential, which puts the block 3 of RAM into read mode and starts the generator 16 impulse!

memory:

hs. Putting the operational unit 3 into read mode provides 30 code combinations of the first character of the attribute to the output of the device, and the pulses from the output of the 16 pulse generator, coming through the OR element 10 to the input of the address shaper 11, provide a sequential change in the addresses of the memory cells in which the code combinations of the second, third, fourth, etc. characters entered. This ensures the issuance of code combinations of the entered characters to the output of the device. As soon as the code combination of the last information symbol of the entered attribute arrives at the output of the device, the next pulse from the output of the pulse generator 16 will provide an overflow signal at the output of the address generator 11, which through the OR element 14 will go to the reset inputs of the adder 6 and counter 8, returning them to the original state. This removes the overflow signal from the output of the counter 8, so the potential is removed from the output of the comparison unit 5 and the pulse generator 16 stops. At the same time, the unit potential is removed from the input of the pulse shaper 12, so a pulse appears at its output, which sets the address shaper 11 to its original state. The appearance of a pulse at the control input of the element PROHIBITION 17 does not affect the operation of the device. Also, the device’s address change is not affected by the change of the address of the read-only memory block 7 when issuing code combinations of the entered characters to the device’s output, since the inputs of the remaining elements of the device do not receive a clock from the output of keyboard 1.

If the operator made a mistake when entering the requisite, then when the control character is entered, a signal will appear on the second output of the comparison unit 5, which, entering the input of the display unit 15, will allow the indication of an error indicator and, simultaneously, through the OR element 14 to the reset inputs of the adder 6 and counter 8, will reset their contents. The transfer of the counter 8 to the zero state ensures the generation of a pulse by the pulse shaper 12, which translates the address shaper 11 into its initial state. The indication of the error sign signals to the operator that an error has been detected in the requisite and must be repeated.

When you enter the following details of the information, the operation of the device is carried out similarly to that described above.

An example of a specific implementation of the prepared data input process. Let the length of props Ι = 9, ξ = 10, to determine the control discharge was used

PVKM type 10 (1,3,9,7). Then, for digital data, for example, of the form 16379245, the prepared requisite will have the form: 163792451. If the operator enters the requisites correctly, then with the input of each character, its code combination is entered into the memory block 3, and the codes of numbers 1 appear sequentially at the output of adder 6; 9; 6; 5; 4; 0; 6 and finally 1, which are formed as follows: when you enter the first ¹ digit, the multiplier immediately transfers its value to the adder 6, since the unit code is stored in the coefficient memory unit at the zero address. When entering the second digit, the multiplier performs the operation 6 x 3 = 18, and the adder 6 performs the operation (18 + 1) mod 10 ~ 9. When entering the third digit, the operations 3 x x9 = 27i (27 + 9) mod 10 = 6 and t .d. If the operator makes a mistake in the process of entering the data attribute, then the control SYMBOLS entered by him and calculated by the device do not coincide and the operator proceeds to re-enter the incorrectly entered attribute.

An advantage of the invention is to halve the time for entering information by the operator.

Claims (1)

Claim A device for inputting information, comprising a keyboard, a register, a random access memory block, a counter, a comparison unit, an indication unit, a first and second OR element, a first delay element, a pulse shaper, the outputs of a keyboard group are connected to the information inputs of the register, the outputs of which are connected to the information inputs of the block RAM and information inputs of the first group of the comparison unit, characterized in that, in order to increase the speed of the device, an address former, a constant memory unit are introduced into it It includes a multiplier, a second delay element, a PROHIBIT element, a pulse generator, a keyboard output connected to a register control input, a counting input of the counter, and through a first delay element to a first input of a PROHIBITION element whose output is connected to the first 10 input of the first OR element, recording input RAM block, controlling the input of the multiplier and through the second delay element with the control input of the adder, the outputs of which are connected to 15 information inputs of the second group of the comparison block, the first output of which is connected to the read input of the RAM block and the input of the pulse generator, the output of which is connected to the second input 20 of the first OR element, the output of which is connected to the clock input of the address shaper, the group outputs of which are connected to the inputs of the read-only memory block and the address inputs of the RAM block 25, the outputs of which are the outputs of the device, the outputs of the register are connected to the information inputs of the first group of the multiplier, the outputs of the permanent memory block are connected to the information inputs of the second group of the multiplier, the output which is connected to the inputs of the adder, the output of the counter is connected to the control input of the comparison unit and the input of the pulse shaper, the output of which is connected 35 to the second input of the FORBID element and the reset input of the address shaper, the output of which is connected to the first input of the second OR element, the output of which is connected to the reset inputs the adder and the counter, the second output of the comparison unit is connected to the input of the indicator and the second input of the second OR element.