SU1295417A1 - Device for determining average value of additive non-stationary random process - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in special computing devices. The aim of the invention is to improve accuracy by increasing its noise immunity and better processing of experimental data. The device contains an analog-digital converter 1, drivers 3, 4 pulses, distributors 6, 9 pulses, counters 7, 8, elements 11, 14, 17, adders 18, 21, registers 24, 27, 30, 32, blocks 16, 19 registers, dividers 28, 31, digital-to-analog converter 29. 1 Il. (L

Description

112954

The invention relates to automation and computer technology and can be used in industrial computing devices.

The purpose of the invention is to increase accuracy.

The essence of the invention is a deeper account of interrelations.

It is obvious that the significant interrelationships of the average value of the additive 10 nonstationary random process (ANSA) should be taken into account within the covariance interval of the latter. In this case, it is necessary to take into account the interconnections in the mean value of ANSA, 5 which is possible by determining the covariance functions, i.e. without the operation centering ANSP. Since in many practically important cases the ANSP covariance interval is less than the covariance interval 20 of its average value, it is possible to determine the relationship of the mean value by the coorse interval of the ANSA.

In the case when the low-frequency deterministic part of the ANSL is a hindrance (for example, it is necessary to eliminate the drift of a zero DC amplifier), the whole procedure is, - 25

stays the same. Further, by the known operation of centering the random process, the low-frequency deterministic part is eliminated.

The number of ordinates of interconnection is determined through the covariance time t, 35 as:

N,

 KO 6

+ 1,

(one)

where At is the quantization interval of ANSP over time

1max

 Gcho-p -

° about + T-) dtdt (2)

where T is the time interval by which the covariance function is determined,

MAI max covariance shift,

x (t),

x (t + T:) - APSP at times t and

(t + d).

in a quantized well-known manner, over time, ANSA on the array of orders N. The auxiliary average values are determined:

17

x./t) S,. (t)

 x, (t) - X, (t)

(3)

Then, the sought average ANSP value is defined as

x (tj

 X, (t) + X (t) + ... + X, -i (t) + X (t)

M

(four)

Subsequent target values are determined recurrently;

x, (t) x, (0 ..M,

(5) where M tO, 9: jC KJ ..

Pa drawing shows a block diagram of the proposed device.

The device contains an analog-to-digital Converter 1, shaper 2 time interval, shapers 3 and 4 pulses, generator 5 pulses, distributor 6 pulses, counters 7 and 8, distributor 9 pulses, a group of elements And 10, element 11, registers 12 and 13, group of elements And 14, adder 15, block 16 of registers, group of elements And 17, adder 18, block 19 of registers, adder 20, adder 21, group of elements And 22, element And 23, register 24, dividers 25 and 26, register 27, divider 28, digital-to-analog converter 29, register 30, divider 31, registers 32 and 33.

The device works as follows.

Before starting work on a given sample object N of the signal x (t) in the former, the covariance interval is determined according to (2). An output signal proportional to T o starts the shaper of 3 pulses of the meander type with Lz 0.9. A falling edge is triggered by a 4-pulse former with L 0.9t. On the leading edge of the pulses with duration X,, 1, a pulse counter 7 is started, where the constant N is determined, and a counter of 8 pulses, where the constant M 0.9N is determined,

Also, the leading edges of the pulses and T trigger the distributors of 6 and 9 pulses. From the corresponding outputs of these pulse distributors, pulses arrive at the control inputs of blocks 16 and 19 of the registers.

permitting passage to block 16 and 19 of the registers, respectively, of the N ordinates of the process x (t) and M values (ordinates) of the local averages x. (t). The device should be considered in stages. To determine the first local average x (t), it is necessary to impose the N ordinates of the process x (t).

This is done by a block of 16 registers.

After determining x. (T), the subsequent local averages are determined recursively according to (3) using groups of elements And 17 and 22 of register 30 and adder 18.

After accumulating 19 registers M of values of local average X; (t) from the distributor 9 pulses, a corresponding pulse is given, the temporary position of which corresponds to the back edge of the pulse1. At the output of the adder 20, the first sought average value x (t) multiplied by M. Accordingly, at the output of the divider 26, on one of the inputs of which the constant M is supplied in binary form, the first sought average value x (t,) is obtained according to (4)

Subsequent values of x (t) are obtained recursively using AND elements 10, 14, register 32 and adder 21. Dp this first x, (t) from the output of divider 26 through register 27 with a delay of At is fed to the first input of adder 21. To the second the input of the adder 21 comes from the output of a group of elements And 10, gated in time by a corresponding pulse from the distributor 9 pulses, the ordinate of the process x (t).

Accordingly, the ordinate of the process x (t) is fed to the third input of the adder 21 from the output of the element gated by the corresponding pulse from the pulse distributor 9.

When adding these three components in the adder 21 at the output of the divider 28, to one of whose inputs in the binary code the constant M from the register 13 is fed, the second desired average value X (t) is formed and will continue until the new definition of the covariance interval T ry. .

Claims (1)

Invention Formula A device for determining the average additive time 2954174 a random process containing an analog-to-digital converter, the first and second counters, the first register, the pulse generator, the clock input of the first register is connected to the output of the pulse generator, characterized in that, in order to improve the accuracy, pulse distributors are entered into it, pulse formers, elements30 15 20 25 35 40 45 50 55 you And, a group of elements And, registers, blocks of registers, adders, dividers, digital-analog converter, shaper time interval, the device input is connected to the input of the analog-to-digital converter, the output of which is connected to the information input of the first block of registers and the input shaper of the time interval, clock input which is combined with the clock inputs of the adders of the second, third, fourth, fifth, sixth, seventh registers, registers of pulse distributors, digital-analogue converter and The first inputs of the first and second elements are connected to the output of the pulse generator, the output of the time interval generator is connected to the information input of the first pulse generator, the output of which is connected to the information pulse, the first input of the second pulse generator, and the first output of the first pulse distributor. which is connected to the inputs of the record of the first block of registers the i-th output of which i (1 - n) is connected to the i-th information input of the first adder, (n + 1) -th input of which is combined with the first input of the second connected to the output of the second register, the information input of which is combined with the input of the divisible first divider and connected to the output of the first adder; the inputs of the divider of the first and second dividers are combined and connected to the output of the first register, the information input of which is connected to the output of the first counter, which is connected to the output of the first element And, the second input of which is connected to the output of the first pulse shaper, the second and third outputs of the first pulse distributor are connected to the first th inputs of AND gates of the first and second groups, respectively, The yields rows are connected to the second and 51 the third bit inputs of the second adder, respectively, the input of the divisible second divider and the information input of the third register are combined and connected to the output of the second adder, the fourth information input of which is connected to the output of the third register, the first and the n-th outputs of the first register block 1 respectively to the second inputs of the elements And, the first and second groups, the output of the second driver. The pulses are connected to the start input of the second pulse distributor and to the second input of the second element And, the output of which o connected to the counting input of the second counter, the output of which is connected to the information input of the fourth register, the output of which is connected to the inputs of the third and fourth dividers, the output of the first divider is connected to the information input of the fifth register, the recording input of which is combined with the recording inputs of the second register unit The ditch is connected to the first output of the second pulse distributor, the second output of which is connected to the first inputs of elements AND of the third group, the second inputs of elements AND of which are connected to the nth output the second register unit and combined with Editor S.Patrusheva Order 619/56 Compiled by I. Mukhin Tehred I.Popovich Proofreader N.Korol Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 13035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 176 The n-th input of the third adder, the third input of the second pulse distributor is connected to the first inputs of elements AND of the fourth group, the second inputs of elements AND of which are connected to the first output of the second block of registers and combined with the first information input of the third adder, the output of the fifth register is connected to +1) -th information input of the third adder, (n + 2) -th input of which is combined with the first information input of the fourth adder and connected to the output of the sixth register, whose information input is connected to the output of the three Its divider, the input of which is divisible is connected to the output of the third adder, the outputs of the elements of the third and fourth groups are connected respectively to the second and third bit inputs of the fourth adder, the fifth information input of which is connected to the output of the seventh register, the information input of which is combined with the information input of the digital-analogue the converter and connected to the output of the fourth divider, the input of which is divisible is connected to the output of the fourth adder, the output of the digital-to-analog converter is output device.