SU938396A1 - Analog-digital converter - Google Patents

Description

(54) ANALOG-DIGITAL CONVERTER

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The invention relates to a pulse technique and can be used in converters included in a registration system for fast processes, as well as in high-speed digital devices.

A conveyor analog-to-digital converter is known that contains comparison blocks, keys, delay lines, an encoder and a voltage adder, with the npe-jg signal being generated being simultaneously applied to the comparison block and the delay line connected to one of the adder inputs. The reference inputs, outputs, and 5 units of comparison units are connected to the second inputs of the comparison units. They are connected to the control inputs of the keys and the encoder inputs, through which the reference voltages with the opposite sign are connected to the second input of the adder.

Each comparator block compares the input signal with its own reference. The values of the standards in the comparison blocks are poured into a predetermined number of quanta, the output signals of the comparison blocks are controlled by the keys, and only the standard is supplied to the input of the adder, COO-Responsible to the triggered block —.-. and the rest of the keys do not work. At the expense of the delay line, the moments of arrival at the input of the adder of the reference and input signals EI are synchronized.

The disadvantages of the converter are low accuracy due to the fact that the input signal passes through the delay line, resulting in a distortion of the signal, and a slow response rate due to the presence of delay lines.

In addition, in this device, synchronization is disrupted due to uneven & ng input to the inputs of the input signal and the reference voltage due to the variation of the parameters of the delay lines reaching 30%.

The closest to the invention to the technical essence is an analogue digital converter (ADC), using the princess on-the-fly strobing. diode array fixed memory, control unit, output register; moreover, the first inputs of the comparators are connected to the dividend. voltages, the second with the control unit, the third with the input of the signal to be converted, the outputs of the comparators are connected to the inputs of the logic elements of the coincidence, the outputs are connected to the diode array. having exits / connected to the output register. The conversion process in such an ADC is to use a set of comparators and an additional logic circuit for an address pulse, which; reads from. Permanent memory desired result. The presence of a gating circuit allows one to set at the output of the asomparator one fikbIrbjnny state irrespective of the change in the input signal between the adjacent gates, and the presence of a trigger memory fixes at the output of the comparator the logical state in which it was at the time of the trigger potential 2, the disadvantages of the Converter ow -. The complexity of the circuit solution due to the presence of a control unit, a fixed memory, which should have all possible combinations in the required order, the ambiguity of the instants of triggering triggers when the enable signal is applied to them, when the same signal acts on the comparator inputs signal, loss of information in the intervals between neighbors, HJ MI gates, as well as low speed. The purpose of the invention is to improve the accuracy and speed of performance of the conversion. The goal is achieved by the fact that the analogue-to-cy (| quad converter containing register triggers, comparators, the first inputs are connected to the outputs of the voltage divider, the second inputs are connected to the input signal bus, and the strokes are connected to the first inputs of the corresponding anti-coincidence elements, the second inputs of which are connected to the outputs of the preceding comparators, and the second input of the higher anti-coincidence element are connected to the common bus, subtracors are introduced;, the element NOT, short pulse shapers, voltage amplifier & ENT, the inputs through the short pulse drivers are connected to the corresponding outputs of the comparators, and the output is connected to the counting inputs of the register triggers, the first inputs of the subtractors are connected to the input bus, the second inputs to the outputs, voltage dividers, the control inputs of the subtractors , besides zero, are connected to the output of the corresponding anti-coincidence element and to the G input of the corresponding register trigger, and the outputs connect to the corresponding inputs of the voltage amplifier, while controlling Zero 1 input is connected to the reader through the element NOT from the output of the first comparator, the bus Reset connected to the R inputs of the register triggers, and the output of the voltage amplifier connected to the transition bus for the next decade. The drawing shows a structural diagram of one decade of the ADC. I. The device consists of a voltage divider 1, comparators 2, elements 3 and an SRI of the HE 4 element, shapers 5 short pulses, an OR 6 element, a subtractor 7 (Uy ... - Ug), register 8 triggers, a voltage amplifier 9. The device works as follows; at one time, the input normalized signal is applied simultaneously to the comparators 2 and the subtractors 7 of the first high decade. Each of the comparators compares the input signal with its own reference. The values of the comparator standards differ by a predetermined number of quanta, which are selected in accordance with the normalized signal. In our case, the quantum is equal to It: 10. If the comparator operates (7 /), then the output signals of THESE comparators go to a chain of elements 3, which convert them in such a way that the output signal corresponding to 1 remains only on one bus corresponds to the highest number of the comparator that worked. This signal is both enabling and informational. Allowing to produce the result of the subtraction (U-Ug) is not the amplifier 9, whose gain factor is 10. Information for the output register 8 The amplified signal is fed to the last decade for further conversion, which is executed in the same way as the older decade, except voltage divider 1, which is common to all decades.

The conversion of the input signal of each decade, the value of which is less than the quantum of the reference voltage, is carried out using a zero subtractor. In this case, none of the comparators work and the first comparator through the element NOT 4 gives permission for. connecting the input signal to the input of a voltage amplifier. Further transformation in the next decade occurs according to the above scheme. To record the signal into register triggers, short pulses are generated by the driver 5 from the voltage level difference when the comparators switch to the logical O or 1. These sync pulses through the OR element to the counting trigger inputs of the register and set the trigger to the state depending on the information on the D inputs.

The accuracy of the conversion is increased due to the fact that only one comparator is triggered in the device for each decade and information is written to the output register. The activated comparator is a gate signal source. In addition, there is a zone of uncertainty in the comparator. When the signal approaches the trigger threshold, an oscillatory process occurs at the output of the ksmparator. In this case, there are great difficulties in reading the code, which are associated with the possibility of errors, such as reading uncertainty. From this point of view, in the device, using a shaper, only one signal is selected corresponding to this moment of switching of the comparator.

In the proposed device, the possibility of information loss between adjacent gates is excluded, as is observed in the well-known one, because comparators continuously monitor the signal when the specified minimum threshold level is exceeded.

In the proposed device, there is no loss of time for performing the subtraction operation, since this process is carried out simultaneously with the comparison, and the difference between the input voltage and the reference / g is always ready to be connected to the input of the amplifier, and all encoding operations are performed simultaneously.

Claims (2)

1. E. Gitis. Information converters for electronic digital calculating devices. M., Energie, 1970, p. 314-318. 2. Foreign radio electronics, 1975, X 1,. P. 88, 89 (prototype). $ -1 ,one 8-1 h n Not cftedytoufyto decade , throttle