SU385317A1 - PERMANENT STORAGE DEVICE WITH TWO MEMORY ELEMENTS FOR A DISCHARGE - Google Patents

Description

one

The invention relates to digital computing and can be used in the storage devices of digital computers.

Permanent memory devices using two memory elements per bit are known. In these devices, the writing of the bit code is carried out by connecting the address bus with each of the t-bit buses in a certain way. If, for example, code 1101 is to be written, then "1 at" O is written to the memory element of each bit, i.e., four operations are performed to record this code.

In the window of the storage core, for example, a transformer permanent storage device, when using on-off recording in a known manner of forward and backward firmware, it is necessary to enter as many code wires as the outputs have a code selector decoder. Increasing the information capacity and reducing the size of the permanent storage device requires an increase in the density of information recording, a reduction in the number of operations and the time of recording and rewriting information.

The disadvantages of known permanent storage devices are the following: low information recording density; a large number of operations when recording and rewriting information;

more time spent recording and rewriting information.

The aim of the invention is to increase the information recording density.

The purpose of the invention is achieved by using write-through circuits " 1 and " O, consisting of " OR and prohibiting circuits, wherein the bit memory for writing " 1 is connected to the prohibiting circuit of the write-through circuit " 1 and the scheme “OR the trigger of the given digit of the number register. The memory element of the bit for writing “O is connected to the prohibition circuit of the write-through circuit“ 1, the circuit ”OR the write-through circuit“ O and the circuit ”OR set to“ On the trigger of this bit of the number register, the prohibition circuit of the write-through circuit ” 1 is connected to the OR circuit of the previous bit of the write-through circuit “1, the circuit” OR is set to “1 trigger of the given bit of the number register and the circuit” OR of this bit of the write-through circuit “1, which is connected to the prohibition circuit of the subsequent circuit discharge pass-through recording “1. The circuit of prohibiting the discharge of the through-write circuit “O is connected to the circuit” OR of the previous discharge of the through-write circuit “O, circuit” OR is set to “About the trigger of the given bit of the number register and the circuit” OR of this bit of the write-through circuit “O that connected to the prohibition scheme

subsequent discharge of the write-through circuit

The drawing shows a diagram of a persistent storage device in which three-bit codes are recorded.

In the permanent storage device, the address register / is connected to address decoder 2. Address bus 3 is connected to memory elements 4, 5 to 6, address bus 7 to memory elements 8 and 9, address bus 10 to memory element 8.

The memory element 8 is connected to the prohibition circuit P of the write-through circuit, “O, to the circuit,” OR 12, the write-through circuit, “1, and to the circuit,“ OR 13, set the trigger of the number 14 register to ”1. The memory element 4 is connected to the scheme "OR 15 of the write-through write chain" O, the prohibition circuit 16 of the write-through write chain "1 and the scheme" OR 17 set the trigger of the number 14 register in "O. The memory element 5 is connected to the prohibition circuit 18 of the write-through circuit "O, circuit" OR 19 of the write-through circuit "1 and circuit" OR 20 set trigger 21 to "1. The memory element 9 is connected to the scheme “OR 22 of the write-through write chain, O, the prohibition circuit 23 of the write-through write chain,“ b, and the “OR 24 set trigger circuit of the 21 number register in“ O.

The memory element 25 is connected to the prohibition circuit 26 of the write-through circuit "O, circuit" OR 27 of the write-through circuit "1 and the circuit" OR 28 set the trigger of the register of the number 29 to "1. The memory element 6 is connected to the OR circuit 30 of the write-through circuit O, the prohibition circuit 31 of the write-through circuit 1 and the circuit OR 32 set the trigger of the number 29 register to O. The memory elements 5, 8, and 25 are for recording “1, the memory elements 4, 6, and 9 for recording“ O. Prohibition schemes //, 18, 26, schemes “OR 15, 22 and 30 form a chain of through recording“ O. The prohibition schemes 16, 23 and 31, the schemes “OR 12, 19 and 27 form a chain of through recording“ 1. The address register 1 is connected to the address channel 33, and the “OR 17, 24 and 32” circuits are connected to the bus 34 in the installation “O. Triggers of the registers of the numbers 14, 21, and 29 are connected to bit buses 35, 36, and 37, respectively.

Address bus 3 contains code 010, address bus 7 contains code 100, and address bus 10 writes code 111, i.e., only bits indicating the change of information are recorded in memory elements 4, 5, 6, 8, 9, and 25. Such bits in the 010 code are all three bits, in the 100 code two high bits, in the 111 code one high bits. Thus, the use of the proposed permanent storage device allows to increase the information recording density. The analysis, for example, of real firmware tables of transformer permanent storage devices indicates the possibility of compressing information several times.

Permanent storage device operates as follows. Before accessing the device from the bus, setting “O 34 to the circuits

“OR 17, 24, and 32 receive a signal that sets the triggers of the registers of the numbers 14, 21, and 29 to“ O. The address register / via address channel 33 receives an address code, which is entered into address decoder 2. An address decoder converts an address code into a position code, according to which one of the address buses 3, 7 or 10 is energized. When excited, for example, the address bus 7, the signal appears at the output of the memory elements 8 and 9. The signal from the memory element 8 is fed through the circuit OR 13 to the trigger register of the number 14 and sets it to 1. On bit bus 35, the signal "1." At the same time, the signal from the memory element 8 goes through the “OR 12” circuit to the prohibition circuit 23.

The signal from memory element 9 enters through the scheme “OR 24 on the trigger register of the number 21

and confirms his condition "O. The “O” signal is removed from the bit bus 36. At the same time, the signal from the memory element 9 is fed to the prohibition element 23, prohibiting the passage of the signal from the OR 12 circuit, and to the

“OR 22 chains through recording“ O.

The signal from the OR 22 circuit arrives at the prohibition circuit 26, and since the signal from the memory element 25 does not arrive at the prohibition circuit 26, the signal from the OR 22 circuit passes through

the prohibition circuit 26 on the circuit "OR 30 to set the subsequent bit in" O and on the circuit "OR 32, the signal with which confirms the state" On the trigger of the register of the number 29. Thus, the triggers of the registers of the numbers 14, 21 and

29 turned out to be set to the state "1," O, and "O and, respectively, with the bit lines 35, 36 and 37, the code" 100 is read, for writing which required two write operations: to the memory elements S and 9.

Similarly, a persistent storage device operates when driving address buses 3 and 10 is excited.

Subject invention

A permanent memory device with two memory elements per bit, whose inputs are connected to the outputs of the address decoder, and the outputs through the “OR set” 1 and “O” circuits to the corresponding inputs of the number register trigger, which in order to increase the density records of information, in it chains of through record "1

and "O, consisting of" OR schemes and prohibition schemes, a memory element for recording "1 connected to a prohibition circuit of a through recording system" O, an "OR circuit of a through recording" 1 and a scheme "OR trigger of this bit

the number register, and the memory element for the record “O is connected to the prohibition circuit of the write-through circuit“ I, the circuit ”OR the write-through circuit“ O and circuit ”OR setting the“ On the trigger of this bit register number, the prohibition circuit loop through chain "1

connected to the “OR previous bit of the write-through circuit“ 1, circuit ”OR set to“ 1 trigger of the given bit of the number register and the circuit ”OR this bit of the write-through circuit“ 1, which is connected to the prohibiting circuit of the subsequent discharge of the pass-through write "1, the prohibition of the yes

the write-through circuit “O is connected to the scheme“ OR the previous bit of the write-through chain “O, scheme“ OR set to “About the trigger of the given bit register number and the scheme“ OR this bit of the write-through circuit, “O which is connected to the circuit the prohibition of the subsequent discharge of the write-through circuit “O.

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