SU377876A1 - FERRITE STORAGE DEVICE WITH LINEAR - Google Patents

Description

one

The proposed device relates to the field of computer technology and can be used in the construction of digital computers.

Line-sampled ferrite memories are known, containing a n-bit array stitched with address and bit buses, playback amplifiers, and a device for temporal selection of output signals (mode selector).

The main disadvantage of the known ferrite memories is their low noise immunity, which is the result of the fact that the read signal "1 in the gate, the discharge has a small amplitude compared with the noise that can rise to it many times.

The aim of the proposed invention is to improve the noise immunity of linear-sampled ferrite chargers.

The goal is achieved by the fact that the ferrite memory contains an additional bus stitched through all the cores of the matrix and connected to the input of the mode selector, and in each card an additional bus is stitched according to the corresponding address bus.

A schematic diagram of the proposed device is shown in the drawing.

The device contains an (G-bit matrix) with two cores per discharge, for example, cores 2 and 3, 4 n 5, etc. All matrix cores are stitched with address buses 6, bits buses 7 and an additional bus 8, which runs in each core according to the corresponding address bus and connected to the mode selector 9. The output of the mode selector 9 is connected to the selection inputs of the playback amplifiers 10.

RA: The bot of the proposed device is implemented in the following manner.

In the recording mode of a single code in the first digit of the first memory address under the action

the address current of the write / ssh and the discharge current / bit of the "1" core 2 is re-magnetized. When this code is read, the iodine by the action of the read current / CHI of the core 2 is re-switched to its original state and

the non-ground output of the auxiliary bus initiates a negative polarity signal. When writing a zero code in this bit, the core 3 is re-magnetized by the current of the / zp1 and the discharge current / bit. In the reading mode, the core 3 is idle and the output of the full bus excites a negative polarity signal, as well as and when reading a single code.

Thus, regardless of the value of the read bit code, a negative polarity signal is excited at the output of the additional bus. Similarly, for other bits of the selected address, the signals of the magnetizable cores in the read mode have a negative zero on the output of the additional bus.

In the second address bus, the address currents have directions opposite to the directions of the e1 address currents in the first address bus. Therefore, when writing a single code, the core 5 is re-magnetized by the core 5, and the core 4 is recorded when the zero code is written. It is easy to see that the signal of negative polarity is excited at the output of the additional bus during reading of any of the cores 4 or 5. Thus, in the read mode, the signals from the remagnetized cores at the output of the additional bus have the same polarity, regardless of the selected address and bits.

Since the cores of the selected address are re-magnetized at the same time in all bits, and the signals from the remagnetized cores have the same polarity, the signal in the additional bus is equal to the sum of the signals of all bits of this address.

In the read mode, the signal from the additional bus passes the mode selector 9, opened by the read mode signal, and as a strobe signal goes to the selection inputs of the playback amplifiers 10, allowing the read signals to go to the output buses of the output O, ..., output .

In recording mode, the read mode signal is absent and the signal from the additional bus through the mode selector is blocked.

In the recording mode, all the discharge cores are under the action of the discharge current, which causes their reversible remagnetization. As a result of this process, noise is excited in the bit lines 7. The magnitude of the interference at the output of the discharge bus (at the input of the playback amplifier W) is equal to the sum of the interference signals excited by all of the discharge cores. In the additional bus, interference from each pair of cores of unselected addresses is compensated. For example, when writing a single code at the first address, the core 4 in the additional bus excites negative interference: polarity, and core 5 - positive polarity, which, when summed, are mutually subtracted. Thus, at the output of the additional bus there are no interferences induced by the discharge current.

Thus, in the proposed device, the strobe signal is equal to the sum of the signals of all simultaneously simultaneously re-magnetized cores of the selected address, the number of which is constant and equal to the number of bits, and this signal is free from the noise excited by the discharge current. The large ratio of the amplitude of the gating signal to the interfering signals increases the reliability of the correct selection of the output signals, as a result of which the reliability of the memory device operation increases.

Subject invention

A ferrite memory, its linear sampling device, containing a two-core split-matrix array per bit, stitched with address and bit buses connected to playback amplifiers, and a mode selector connected to selector inputs of playback amplifiers, characterized in that , in order to improve noise immunity, it contains an additional bus, stitched through all the cores of the matrix and connected to the mode selector input, and in each core an additional bus is stitched according to address bus.

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