JP2531296B2 - Serial access memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a serial access memory (hereinafter referred to as SAM) which has high speed, low power consumption, a wide operation margin, and does not require a highly sensitive sense amplifier. is there.

[Conventional technology]

FIG. 3 is a block diagram of a conventional SAM. In the figure, (1) is a write bit line, (2) is a read bit line, (3) is a write word line, (4) is a read word line, and (20) is necessary to use a sense amplifier (19). Inverter for generating differential signal, (6) MOS access transistor of read bit line (2), (8) address pointer, (9) output buffer, (10) power supply, (11) Is output, (12) is dynamic memory cell, (13) is GND, (14) is capacitor,
(15) is a MOS precharge transistor, (16) is a MOS
Is a memory transistor, (17) is a MOS read transistor, and (18) is a MOS write transistor. The memory cell (12) includes a memory transistor (16), a read transistor (17), a write transistor (18), and a capacitor (14).

Next, the operation will be described. Writing information "X"
The potential of the selected write word line (3) becomes "H", the write transistor (18) connected to the selected write word line (3) becomes ON, and the potential of the write bit line (1) becomes "X". "Is performed by charging or discharging the capacitor (14). After that, even if the writing transistor (18) is turned off, the information is normally held in the capacitor (14) for several hundred milliseconds.

Regarding the written information, the potential of the read word line (4) becomes “H”, and the read transistor (17) is turned on.
Then, information is transmitted to the read bit line.

Next, the operation of the precharge transistor (15) will be described. When the storage information “X” is “L”, the storage transistor (16) is OFF, so the read bit line (2) is connected to the GND (grounded) via the read transistor (17) and the storage transistor (16). Line) (13) not connected to the power supply (power line) through the precharge transistor (15)
Due to the electric charge supplied from (10), the potential of the read bit line (2) becomes "H". When the stored information is "H", the read transistor (17) and the storage transistor (1
6), all the precharge transistors (15) are turned on, but the read transistor (17) and the memory transistor (16) usually have a larger capacity than the precharge transistor (15). , The potential of the read bit line (2) becomes "L".

The potential of the read bit line (2) is set to the sense amplifier (19).
Senses level. The logical amplitude of this read bit line (2) is Here, V _CC is the voltage of the power supply (10), V _TH is the threshold voltage of the precharge transistor (15), R ₁₅ , R ₁₆ and R ₁₇ are the precharge transistor (15) and the storage transistor ( 16), because it is the ON resistance value of the read transistor (17), "H" is the power supply (10) and voltage V _CC , and "L" is GND.
The voltage of (13), that is, not equal to the ground potential, has a narrow voltage difference (logical amplitude) between "H" and "L".

Since the logic amplitude is narrow, the sense amplifier (19) needs to have high speed and high sensitivity. The differential signal required for the sensing operation is generated by the inverter (20).

A plurality of memory cells (12) are connected to each read word line (4), and all the memory cells (12) connected to the read word line (4) are read by being set to "H". . The read bit line (2) to which the memory cell (12) to be read is connected is selected by the address pointer (8) which operates according to the clock. Further, the sense amplifier (19) senses the signal of the read bit line (2), the output buffer (9) latches, and outputs (11) as the signal Q.

[Problems to be Solved by the Invention]

Since the conventional SAM is configured as described above, all the precharge transistors corresponding to the number of read bit lines are always on, and writing "H" to all memory cells consumes a large amount of power. When the power of the precharge transistor is lowered due to low power consumption, it takes time for the output to invert to "H", and the memory size increases when the memory transistor and the read transistor are increased. Also, since the precharge transistor is always on, it takes time for the output to reverse to "L".

As described above, the potential "H" of the read bit line is (V _CC
−V _TH ), which is not equal to the power supply V _CC , “L” is obtained from the ON resistance of the memory transistor, read transistor, and precharge transistor, and cannot be equal to GND. Become.

Therefore, it is necessary to perform a sensing operation by a highly sensitive sense amplifier, but for that purpose, a differential signal is required, and it takes time to generate the differential signal. Furthermore, if the sensing operation is performed at high speed, the timing margin becomes severe.

As described above, the conventional SAM consumes a large amount of power, has a slow operation speed, and requires a high-sensitivity sense amplifier.

The present invention has been made to solve the above problems, and does not require the high-speed and high-sensitivity sense amplifier shown in FIG. 3 described above. The objective is to realize a SAM with low power consumption and a large read bit line logic amplitude.

[Means for solving the problem]

In the SAM according to the present invention, the memory content selected by the write word line at the time of writing is written with the stored content of the data transmitted to the write bit line, and the read word line different from the write word line at the time of reading is selected. In a serial access memory in which memory contents are read from a memory cell to a read bit line different from the write bit line, all the precharge transistors for precharging the potential of the read bit line are not in the conductive state, but read At the same time, when the address pointer selects one of the read bit lines, the precharge transistor connected to the read bit line next to the selected read bit line is selected and brought into the conductive state. It was done.

[Operation] In the present invention, the address pointer simultaneously selects one of the read bit lines and the precharge transistor connected to the read bit line to be read next to the selected read bit line, and performs the read operation. When the memory cell stores the "L" level at the time of selection, the potential of the read bit line can be set low, and the precharging transistor can be selectively turned on to reduce power consumption.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (1), (4), (6), (8) to (12)
Is the same as that shown in the conventional example of FIG. (5) is an inverter that doubles as a sense amplifier,
(7) is a MOS precharge transistor. The inside of the memory cell (12) is similar to that shown in FIG.

 Next, the operation will be described.

When writing to the memory cell (12), the potential of the selected word line (3) becomes “H” level, the writing transistor (18) connected to the selected writing word line (3) is turned on, According to the data to be written, that is, the level of the write bit line (1), the capacitor (14) in the memory cell (12) is charged or discharged to write the data. The potential of the selected write word line (3) becomes "L" level, and the write transistor (18) becomes
Even if the capacitor is turned off and the capacitor (14) is electrically floated, the capacitor (14) retains data for several hundred milliseconds.

Next, when reading from the memory cell (12), the potential of the selected read word line (4) becomes “H” level, and the read transistor (17) connected to the selected read word line (4) Turns on, but when the data in the capacitor (14) is "L", the memory transistor (16) is turned off.
Therefore, the read bit line (2) is connected to GND via the read transistor (17) and the memory transistor (16).
The electric potential of the read bit line (2) becomes "H" level due to the electric charge which is not connected to the (ground line) (13) and is supplied from the power source (power line) (10) through the precharge transistor (7). Become. When the data of the capacitor (14) is "H",
Since the storage transistor (16) is turned on, the read bit line (2) is connected to the GND (13) via the read transistor (17) and the storage transistor (16), and the potential of the read bit line (2) Goes to "L" level.

Since the read transistor (17) and the memory transistor (16) have a higher capacity than the precharge transistor (7), the precharge transistor (7) is turned on.
However, the "L" level of the read bit line (2) is maintained.

The precharge transistor (7) is selected by the address pointer (8), and only the selected one makes the power source (10) and the read bit line (2) electrically connected to each other, and the power source (10). ) Is precharged to the read bit line (2) electrically connected to the read bit line (2). The data of all the memory cells (12) connected to the selected read word line (4) are read to the corresponding read bit line (2). The level of the read bit line (2) at this time is as follows.

That is, as will be described later, the precharge transistor (7) is controlled by the address pointer (8) so that the one corresponding to the column to be accessed next is turned on. The level of the read bit line (2) arranged in the column is almost GND when the data written in the memory cell (12) connected to the read bit line (2) is "H". It becomes the "L" level which is the same level as the potential of (13), and when it is "L", it becomes the "H" level (V _CC -V _TH ) and it is arranged in the column to be accessed next by the address pointer (8). The read level of the read bit line (2) is selected by the address pointer (8) when the data written in the memory cell (12) connected to the read bit line (2) is “H”. hand A precharge transistor (15) and a memory transistor (16) that are made conductive.
And the "L" level based on the ON resistance value of the read transistor (17), and when it is "L", the precharge transistor (15) selected by the address pointer (8) and brought into the conductive state is used. Precharged to "H"
The level of the read bit line (2) becomes the level (V _CC −V _TH ), and the data written in the memory cell (12) connected to the read bit line (2) is “H” at the other levels. , It is almost at the same level as the potential of GND (13) and is "L" level, and when it is "L", it is undefined, that is, the data written in the memory cell (12) read previously is It is a dependent level.

The precharge transistor (7) connected to the read bit line (2) and the read bit line (2) to be accessed next is selected by the address pointer (8) set by the clock. The level of the selected read bit line (2) is obtained by the same method as the conventional method, but when the precharge is completed, the precharge transistor (7) is turned off, and the level of the read bit line (2) at this time is written. When the stored data is "H", it is almost equal to the level of GND (13). When the data is "L" (V _CC -V _TH ), the precharge transistor (7) is turned off but the level is " Held in H ". Therefore, the logical amplitude becomes large.

The above operation will be described with reference to the timing chart of FIG. During the period from t ₁ to t ₂ of the clock, the output node _{Am-1 of} the address pointer (8) becomes "H" level and the read bit line (2) arranged in the m-1th column is accessed. At the same time, the precharge transistor (7) connected to the read bit line (2) arranged in the m-th column (the final column in this embodiment) is selected,
Precharge is performed. During the period from t ₂ to t ₃ , the output node Am of the address pointer (8) becomes “H” level, and the read bit line arranged in the m-th column precharged in the period from the previous cycle t ₁ to t _2. (2) is accessed and at the same time, connected to the read bit line (2) arranged in the 0th column (the first column in this embodiment) to be accessed next in the interval from t ₂ to t _3. Precharging is performed via the precharged transistor (7).

In the above embodiment, the memory cell (12) has a configuration of 3
The case of using one transistor and one capacitor has been described, but the structure is not limited to the structure of the memory cell (12) in the above embodiment as long as the write and read ports exist independently.

〔The invention's effect〕

As described above, according to the present invention, since only one precharge transistor is turned on, even if this capability is increased, the influence on power consumption is small. Also, the output data is inverted to "H" faster, and the precharge transistor is OFF when the read operation is being performed. Therefore, when "L" is output, only the level of the read bit line is sensed. , And it becomes faster to reverse to "L". Also, the "L" level becomes almost equal to the GND level, the logic amplitude becomes large, and the high-sensitivity sense amplifier can be substituted with an inverter, so that delicate timing is not required. From these, there is an effect that a SAM capable of high-speed reading can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a memory section and read control of a SAM according to an embodiment of the present invention, and FIG. 2 is a read bit line and precharge operation selected by a clock and an address pointer in the SAM of FIG. FIG. 3 is a block diagram showing the structure of a conventional SAM, which shows the relationship of FIG. In the figure, (1) is a write bit line, (2) is a read bit line, (3) is a write word line, (4) is a read word line, (5) is an inverter, (6) is an access transistor, and ( 7) is a precharge transistor, (8) is an address pointer, (9) is an output buffer, (10) is a power supply, (11) is an output, and (12) is a memory cell. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takahiko Komatsu 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Semiconductor Software Co., Ltd. Kita-Itami Works (56) Reference JP-A-4-355297 (JP, A) ) JP-A-62-43894 (JP, A)

Claims (5)

(57) [Claims] 1. A plurality of write bit lines, a plurality of read bit lines different from the plurality of write bit lines, a plurality of write word lines, and a plurality of read word lines different from the plurality of write word lines. A plurality of dynamic memory cells composed of three types of MOS transistors for writing, reading and storing, and a plurality of precharging MOS transistors connected to each of the plurality of read bit lines. A plurality of sense amplifiers respectively connected to the plurality of read bit lines; a plurality of read bit line access MOS transistors respectively connected to the plurality of read bit lines; It is equipped with an address pointer that operates with a clock. One of the plurality of read bit line access MOS transistors described above is brought into a conductive state, and a read bit line access MOS transistor selected next to the selected read bit line access MOS transistor is selected. MO for precharge connected to the connected read bit line
A serial access memory characterized in that S transistors are selected at the same time to make them conductive. 2. A plurality of write bit lines arranged in a plurality of columns, a plurality of read bit lines arranged in a plurality of columns, a plurality of write word lines arranged in a plurality of rows, and a plurality of rows. A plurality of read word lines, which are arranged in a plurality of rows and a plurality of columns, each of which is connected to a write word line and a read word line which are arranged in a corresponding row, and a write bit line which is arranged in a corresponding column. And a plurality of dynamic memory cells connected to the read bit line, a plurality of precharge transistors arranged in a plurality of columns and connected between corresponding read bit lines and power supply lines, and the plurality of read bits Select one of the lines and connect the precharge transistor connected to the read bit line selected next to the selected read bit line. Serial access memory having an address pointer to the static, conductive in selected simultaneously with the read bit line is selected. 3. A plurality of write bit lines arranged in a plurality of columns, a plurality of read bit lines arranged in a plurality of columns, a plurality of write word lines arranged in a plurality of rows, and a plurality of rows arranged in a plurality of rows. A plurality of read word lines, arranged in a plurality of rows and a plurality of columns, each connected to a write word line arranged in a corresponding row and a read word line arranged in a corresponding row, and corresponding to a corresponding column. A plurality of dynamic memory cells connected to a write bit line arranged in a column and a read bit line arranged in a corresponding column; a read bit line arranged in a plurality of columns, each arranged in a corresponding column And a plurality of precharging transistors connected between the power supply line and the power supply line, each of which is connected to a read bit line arranged in a corresponding column and arranged in a corresponding column. A plurality of sense amplifiers for amplifying and outputting the potential appearing on the read bit line, a plurality of sense amplifiers arranged in a plurality of columns, each connected between the output of the sense amplifier arranged in a corresponding column and the output line Read bit line access transistor of a plurality of columns, each of which has a plurality of output nodes connected to the control electrode of the read bit line access transistor provided in the corresponding column, and the final column The output node corresponding to the column other than is connected to the control electrode of the precharging transistor disposed in the column next to the corresponding column, and the output node corresponding to the last column becomes the column corresponding to the first column. A serial access memory having an address pointer connected to a control electrode of a precharge transistor provided. 4. The serial access memory according to claim 3, wherein each sense amplifier is an inverter. 5. Each dynamic memory cell is connected between a write bit line arranged in a corresponding column and a storage node, and a control electrode is connected to a write word line arranged in a corresponding row. A read transistor in which one main electrode is connected to a write transistor and a read bit line arranged in a corresponding column, and a control electrode is connected to a read word line arranged in a corresponding row, and the read transistor 5. The storage transistor according to any one of claims 2 to 4, wherein the storage transistor is connected between the main electrode and the ground line on the other side of the storage transistor, and the control electrode is connected to the storage node. The serial access memory described in.