SU1203527A1 - Device for generating data address - Google Patents

Description

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The invention relates to computing and can be used in computer systems to form data addresses.

The aim of the invention is to increase the reliability of the device by preventing access to the address space of the dynamic area during exchange with the area of special structures,

In the proposed device, the data located in the dynamic area 5 is protected against erroneous access to them during the exchange with the area of special structures,

The drawing shows the functional diagram of the proposed device. The diagram shows block 1 and shows its connection with the device

The device for generating the data address contains the first 2 and second 3 registers of the address 5 counter 4, the first 5 and second 6 multiplexers j switch 7, the first 8 and second 9 blocks of elements I, the group of input inputs 10.1-10. containing control inputs for selecting address 11, 1 e by transmitting address IKZ with synchronization 11оЗ, first 11.4 and second 11.5 tzhody control of account and data input 11.6 for controlling data transfer, access 11 about 7 for address control, and codes 11.8 for data selection control, group of installation inputs 12, a group of information input rows 13.1 - 13 m, group of information outputs 14, first 15.1 and second 15.2 outlets 15 of the first group of outputs multipolarity 5 leksora first 16.1 and 1.5 second. The codes of the group of address outputs 16, the group of inputs - codes of 17e

The device can operate in two modes: the formation of the address by external subscribers - the sources of the addresses to the inputs 10–1 10.and (and - the number of subscribers of the address sources) | Formation of the address with the counter 4 when working with the stack array or list.

The first mode. In the initial state, all the memory elements are set to the zero state (the inputs of the initial installation are conventionally not shown),

In this mode, the recording or recording of data in (from) block 1 can be made. At the same time, the signal is not on. Inputs 11.2 J 11.4, 11.5 and 12 absence

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stand by. Groups of inputs 10.1 - 10, p. Receive address codes from external subscribers of sources of the address.

The selection of the corresponding input group 10, t (i, e) is carried out according to the setup code from the Input group 11 about 1 multiplexer 5. The selected address is assigned to the input group 15.1 of register 2 2, the youngest (younger) one group of inputs 15 „2 registers 3.

After this, the signal from input 11.3 records this information into registers 2 and 3, respectively. "Output signals of register 2 through switch 7 are fed to the inputs of 16.2 bits of the group of address inputs 16 of block 1"

From outputs 16.1 of register 3, the code of the higher (lower) bits of the data address is also fed to the inputs of the corresponding bits of block 1.

If it is necessary to record data in block 1, then the control code from inputs 11.8 selects one fault of groups of inputs 13., J (J e 1, H1) data (t is the number of subscribers - data sources) o Data from the selected subscriber are sent to the group informational unit inputs of unit 8 from the multiplexer 6 outputs

In this case, the signal at input 11 "6 is absent, which corresponds to the recording mode.

Therefore, the block 8 of the elements AND is open, the data code from the input 13. J is fed through the multiplexer 6 and the block 8 to the group of inputs 17 of the memory block 1 and the signal from the input 11.7 of the device inputs 11 of the device is recorded in block 1 at the address specified on the group inputs 16.

When issuing (reading) data from block 1, the signal at input 11.6 is equal to one. Therefore, the block 8 is closed, and the block 9 elements And open.

When signals are received from input 11 "7, data is output from block 1 at the address specified on inputs 16 along the circuit: output group 17 of block 1, block 9 of the elements I, group of high presses 14 of the device.

A feature of the operation of the device is that the formation of the next data address by multiplexer 5 and reading (writing) data: from (c) block 1 to the address stored in registers 2 (counter 4) and 3j can be performed in parallel.

Further, the device operates in the first mode as described.

Second mode. The transition to the second mode can be carried out mainly for two reasons: if it is necessary to process an interrupt or exchange data with a stack, a list or an array located in the area of special structures.

In both of these cases, the initial contents of counter 4 can be both zero and non-zero.

The operation of the device in this case can be organized, for example, as follows. For each program, it is assigned its own address of the working area, which, before starting to work with the data of the special structure of this program, is entered from the inputs of the group of inputs 12 into the counter 4. After that, the device can switch to the stack operation mode (array, list). a control signal that transfers the register 3 to the third state and, in addition, configures the switch 7 to connect the inputs of the counter 4 with the group of inputs 16.2 of block 1,

In this case, the sample (write) of the number from (c) of the stack (array) is performed at the address specified by counter 4 and register 3, the contents of which do not change during the exchange with this structure. The sampling of numbers in the structure can be carried out in order of increasing or decreasing addresses. The difference is that in the first (second) case, each successive address is formed by increasing (decreasing) the content of the counter by 4 with a signal from input 11.4 (11.5) of the group of inputs 11 of the device.

The operation of the blocks 1,6,8 and 9 is similar to that described for the first mode of operation of the device.

Interrupt handling by the device can also be done using

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calling counter 4. For this purpose, in the area of special structures of block 1, an area is reserved for the placement of a stack of words of the state of interrupted programs.

In this case, the starting address of this area is set as described in counter 4.

When an interruption occurs, the interrupt processing program initiates a high-level processor control of a signal at input 11.2, through which counter 4 is connected to the generation of the address.

The signal from input 11.4 increases the content of counter 4 by one. The status word of the program to be stopped is selected by the multiplex-IpoM 6 with the specified input group 13.J (je 1, m). The signal at input 1.6 is absent, therefore, the signal from input 11.7 records the state word from the outputs of multiplexer 6 through block 8 and group of inputs 5 to block 1. After that, the device continues to function as described for the first mode,

Upon completion of the execution of the interrupted program, a return to the continuation of the interrupted program is made. To do this, the signal from input 11.2 again connects to the formation of the address counter 4, the contents of which are reduced by the signal from input one, and then the signal from input 11.6 reads the state word of the interrupted program from block 1 to the group of outputs 14 of the device.

Further, the device operates as described.

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The depth of the interrupt attachments is determined by the capacity of the counter 4.

The device stops functioning when the controlled signals are removed from the inputs of the bits of the group of inputs 11.

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Editor 0. Yurkovehusa

Order 8418/52 Circulation 709 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

Compiled by G. Ponomareva

Tehred A, Boyko Proofreader; L. Patay

Claims (1)

A device for forming a data address, comprising first and second multiplexers, first and second address registers, a counter and a switch, the group of address inputs of the device being connected to the group of information inputs of the first multiplexer, the first group of outputs of which is connected to the group of information inputs of the first address register, information group the device inputs are connected to the group of information inputs of the second multiplexer, the group of outputs of the second address register is connected to the first outputs of the address group device outputs, address selection control inputs, address selection control inputs, address transfer control input and first account control input of the device control input group are connected respectively to the control input group of the first and second multiplexers, the switch control input and the counting totalizer input, the output group of which is connected with the first group of information inputs of the switch, characterized in that, in order to increase its reliability, it additionally contains the first and second oki elements And, moreover, the synchronization control input group of control inputs of the device is connected to the synchronization inputs of the first and second address registers, the address transfer control input ^ the second account control input and the data transfer control input of the group of control inputs of the device are connected respectively to the control input of the second address register, countable subtracting counter input and inverse control input of the first block of elements AND, Q group of outputs of which is connected to a group of inputs - outputs of the device and g by the group of information inputs of the second block of AND elements, the group of outputs of the second multiplexer is connected to the group of information inputs of the first side of the AND elements, the data transfer control input of the group of control inputs of the device is connected to the control input of the second block of elements AND, the output group of which is a group of information outputs of the device, a group of installation the device inputs are connected to the information inputs and the counter synchronization input, the group of outputs of the first address register is connected to the second load sing information inputs switch group which is connected to the outputs of the second group of address output device outputs the second group of outputs per ·· Vågå multiplexer bonded to the group of information inputs of the second register address.