SU801101A2 - Logic storage - Google Patents

Description

(54) LOGICAL STORAGE DEVICE

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The invention relates to computing and can be used in the construction of discrete information storage devices.

According to the main auth. No. 490183 a logical storage device (LZD) is known, containing a register of reference signs, numeric lines, write write, read and read write buses, which write and read linear buses are connected via the OR elements and the bit elements, respectively, through the reading amplifiers to the inputs of the regeneration register and through the address write and read drivers to the outputs of the address elements AND, whose control inputs are connected through the control elements OR to the control buses, under Switched to the control inputs of the bit elements AND, and auxiliary bit elements AND, the functional inputs of which are connected to the outputs of the regeneration register, the outputs are connected to the bit elements OR, interrogation bus, linear elements Disable by the number of device bits, output element OR, inputs which are connected to the outputs

amplifiers of reading, and the output to the functional input of the element I, whose control input is connected to the interrogation bus, the functional inputs ix (... n) of the linear and discharge elements of the Inhibit and (n + 1) -th, (n + 2) ) -th linear elements of the ban are connected respectively to the outputs ix and () -th, (n + 2) -th bits

0 register of features for the control, the control inputs of the iX of the bit and linear elements of the Inhibit and (n-fl) -ro, (n + 2) -th linear elements The ban is connected to the corresponding discharge and linear control buses, the output of each linear element Zap The ret is connected to the outputs of the two address elements AND of the corresponding numerical line, the output of each bit of the dam element The ban is connected to the input of the corresponding bit element OR 1.

The disadvantage of this LZU is its low speed.

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The purpose of the invention is to increase the speed of LZU.

The goal is achieved by the fact that the proposed device contains dvuhvhodovye switches on the number

0 steps of the regeneration register, the first inputs of which are connected to the control bus, the second inputs and outputs are connected respectively to the output of the corresponding register register bit and to the additional blocking input of the Disable.

The drawing shows a structural scheme of LZU,

The RAM contains drive 1, consisting of numerical lines 2 on toroial cores 3 with a rectangular hysteresis loop, having separate write buses 4, reads 5 and reads b, and linear write buses 7 and reads 8.

Each of the write write 4 write buses 5 and each of the linear write 7 and read 8 are connected to the outputs of the corresponding bit write drivers 9 and read 10 and address writers of the write 11 and read 12. The input of each address writer of the write and write is associated the output of the address element AND 13 or 14, the control inputs of which are connected respectively to the outputs of the control elements OR 15 and 16. The functional inputs of the address elements AND 13 and 14 of the write and read circuits of each numerical line 2 are connected to the output of the corresponding linear element of the ban 17. The functional inputs ix (, n) of the linear and the bit elements of the ban 17 and 18 are connected to the output of the i-th bit of the register 19 of the reference signs, and their control inputs are connected respectively to the linear 20 and the bit 21 control tires.

The functional inputs of the (n + 1) -th and (n + 2) -th linear elements. The prohibition 17 is connected to the outputs of the (n + 1) -th and (n + 2) -th bits of the register, respectively, and 19 These inputs are connected to control line bus 22.

V111 power inputs of bit elements And 23-26 are connected to control buses 27-30. The functional inputs i-x of the bit elements AND 23, 25 and 24, 26 are connected respectively to the inverse and direct outputs of the i-ro bit of the register 31 words. The outputs ix of the bit elements AND 23 and 24, the bit elements of the Inhibit 18 and the auxiliary bit elements AND 32 are connected to the inputs of the bit elements OR 33, and the outputs ix of the bit elements AND 25 and 26 and the elements And 34 are connected to the inputs of the elements OR 35 i-th bit circuit. The outputs of the i-x elements. OR 33 and 35 Lodklyucheny respectively to the inputs of the bit shapers read 10 and write 9.

The control inputs of the elements 32 are connected to the control bus 36.

And 34 elements with a control bus 37. The functional inputs of the i-x elements 32 and 34 are connected to the output of the i-ro bit of the regeneration register 38, and the input of this register is connected to the output of the i-rc reading amplifier 39 connected to the bus 6 of the i-bit circuit. The control inputs of the reading amplifiers are connected to the strobe bus 40, and their outputs are connected to the output buses 41 of the logical storage device and to the inputs of the output element OR 42, the output of which is connected to the functional input of the element And 43. The control input of the element And 43 connects with the reset bus 44, the inputs of the control elements OR 15 and 16, respectively, with the tires 29,30,37 and 27, 28, 36 of the control.

Registers 19 and 31 have tires 45 and 46 shift, register 38 regeneration reset 47, ie, (n + 1) -th and (n + + 2) - and register bits 19 - input tires 48 and 49, register 31 words input busses 50. The first inputs of the two-input switches 51 are connected to the control bus 52, and the second input and output of each i-ro (i-1, n) of the switch are connected respectively to the outputs of the i-ro bit of the regeneration register 38 and to the auxiliary prohibitory input of the bit elements of the prohibition 18.

Denote the value of the i-ro bit binary code stored in the numerical line U; the signal value in

The 1st discharge circuit is X |. The result of the logical operation f (X (; Y, -), which remains in the numerical scale, PJ) is the result of the logical operation CI5 (x.y-) f which is formed on

i-th bit bus 6 reading, 0 ,. Logical operations performed

in logical storage

are shown in the table.

The device works as follows.

Prior to operation, the binary priority code AJ 2 -1 is written into each i-th numeric ruler of accumulator 1, and the priority code A is stored in the (n +1) -th, (n + 2) numeric rulers, and the priority code is written on the regeneration register Aj i-ro is the significant digit of the binary number -В-.

In the first clock cycle, the input code 48 enters the reference feature register with the binary number code

In the second cycle, control signals 20, 22, 28, 52, gating 40 and interrogation 44 are given single signals.

At the same time, the i-e, (n + 1) -th, (n + 2) -th linear elements The prohibition is closed. Part of. Disabled elements 18, each element of which corresponds to 1 bits of priority code A (stored on register 38

regeneration, closed. The remainder of the elements of Prohibition 18 is in a conducting state.

E. Initial signals from the outputs ix (isk ,, ... m) of the register of signs of circulation through the corresponding, not closed by the signals from the switches 51, the bit elements The prohibition 18 and the associated elements OR 33 excite ie readout drivers 10. On reading buses 6, a binary code appears corresponding to the result of operation B „LA | which is fed to the inputs of the reading amplifiers 39. The output signals of the reading amplifiers are fed to the inputs of the OR 42 element, and the signal from its output to the functional input of the output element AND 43, at the output of which the value of V is formed.

The control of the operation of the logical memory in the third cycle is organized depending on the value of the value of Y.

If, then in the third clock cycle, the contents of register 19 are reset to O and the logical memory device returns to its original state.

If the value Y, formed in the second cycle, is equal to one, then in the third cycle the sign AJJ of the k-th digit of the number of Vz is formed, for which single signals are sent to the control line buses 22, 27 and the gates bus 40, and control - zero signals. As a result, single signals Note e.

from the outputs (, f, ... t) of the register of signs of circulation through i-e) the linear elements of the prohibition 17 and the address elements And 14 are fed to the inputs of the corresponding i-x (, J, ... m) address fairformers 12, sshits. and the single signals from the inverse outputs of the register bits of the word are passed through the open elements AND 23 and the elements OR 33 to the inputs of the bit former 10 read.

B (,, ..., m) numerical rulers perform the operations R-OlU (and Q; Y; do, and on the resolution tires 6)

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reading a code of number is formed, $; L

f

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-.and nvif

which is recorded from the outputs of the reading amplifiers in the regeneration register 38 and is fed to the output buses 41.

In the fourth cycle for the first bit of the register of the word and in all bits of the register of signs of circulation is entered

0 units.

a) Afterwards, the (+4) th (, n) clock cycle on shift buses 45 and 46 of registers 19 and 31 and single signals are sent to bus 30 of the control line. As a result, units are recorded in each i-th bit of the i-th to the (n + 2) -th number bars, in the (n + 4) beat in the 1st (, n)

A numeric ruler forms the code A. 2-1, and in (n + 1) -th and (n + 2) -th numeric lines 2 - the code of the number (2 -1).

In the (n + 5) cycle, a reset is made to the O code of registers 19, 31 and the logical memory goes back to its original state. The symbols L denote the operations of prohibition, implication, Pierce arrow, disjunction and conjunction, respectively.

Claims (1)

Claim Logical storage device by auto No. 490183, distinguished by the fact that, in order to improve performance, it contains two-input switches according to the number of bits of the regeneration register, the first, the inputs of which are connected to the control bus, and the second inputs and outputs are connected respectively to the output the corresponding discharge of the regeneration register and to the additional prohibiting input of the discharge elements Prohibition.