SU368643A1 - LOGICAL STORAGE DEVICE - Google Patents

Description

one

The device relates to computing, can be used to build systems for processing and storing discrete information.

A logical storage device is known, which contains a drive with numerical lines on cores with BCPs stitched with discharge and address write and read buses connected to discharge and address formers of a write, read and read, register word, register sign of match; reading amplifiers, address and bit gates and elements "OR.

In the known memory, operations are performed between operands, one of which is in the word register, and the other in the selected accumulator number line. In one cycle of circulation in such a logical memory, it is possible to obtain in the selected numerical range the results of operations of conjunction, disjunction, implication or prohibition. Simultaneously, signals are removed from the output reading buses, corresponding to the execution of the logical interdiction operations, the Pierce arrow, or the conjunction.

The purpose of the invention is to expand the functionality of the device. It is achieved by the fact that each bit of the proposed device contains a delay element, two output valves and two zero and single word trigger inputs, the output of the reading amplifier is connected to the input of the delay element, and the output of the delay element is connected to the word trigger valves , and the word trigger outputs through the output valves are connected to the output terminals of the device.

The block diagram of the device is depicted in the drawing.

The device contains a drive 1 with numerical lines 2 on toroidal cores 3 with BCPs stitched with write bit buses 4, read word buses 5, read bit buses 6, address write buses 7, and address read lines 8. The circuit also contains bit drivers records 9, bit drivers for reading 10, bit elements OR 11, bit valves 12, word register triggers 13, word trigger zero input 15, word trigger single input 16, delay elements 17, output valves 18 s in outputs 19, read amplifiers 20, output valves 21 with outputs 22, control elements OR 23, inputs 24, reset bus 25, reference sign register 26, triggers 27, address gates 28, addressable

write drivers 29, address read drivers 30 of control bus 31-40, inputs 41.

In the initial state in the register of the word 14

the input word X is stored (Xp, ..., Xg, ..., Xi),

and in each numerical line 2 there is some word Y (yn, ..., g / y, ..., g / i), where Xg is the 1-bit word of the input word stored in the i-th trigger of the 13th register words 14; g /, is the i-th bit of the word, stored in the i-th core 3 of the given numerical ruler 2 of the accumulator; n is the number of bits.

The trigger 27 of the reference characteristic register 26 of the numerical rule 2, in which the logical operation is performed, is set to state "1.

Any logical operation on the input word and the word in the selected cell is performed when signals are sent to certain control buses 31-40. For example, when a signal is sent to the pin 36, the signals from the direct outputs of those flip-flops 13 of the register of word 14, which are in the state "1," through the discharge valves 12 and the discharge elements "OR 11, arrive at the inputs of the discharge drivers 9. These signals may be referred to as bit drive signals.

Let Xg 1 denote the excitation bit signals from the inverse outputs of the trigger 13, which are in the state "1", and Xi the l-bit excitation signals from the inverse outputs of the trigger 13, in the state of "O."

Logical operations on words are bitwise operations; therefore, it suffices to consider the implementation of a logic operation in one bit section.

Let P denote the implementation by the tth toroidal core 3 of the selected numerical line 2 of the switching function, the value of which corresponds to the states of this core after being subjected to the discharge signal Xi or Xi, provided that the initial state of the core corresponds to g / g; by gi we denote the implementation (-with the toroidal core 5 of the selected numerical ruler 2 of the switching function, the values of which are obtained on the i-th read bit bus 6 as a result of the discharge signal r; or Xi on the given core with the initial state of u, and the qi function corresponds to the presence of a pulse signal on the i-th bit read bus 5, and zero to its absence; by g, we denote the switching function obtained on the output 19 slots, the value of which is determined by the state of the trigger 13 of the register words 14 after acting on its zero or single signal input from the output of the delay element 17.

Logical operations that can be performed in the proposed logical memory,

are shown in the table. As an example, let us consider the execution of logical operations of the conjunction Lg, the prohibition gi yiAxi and

DISCONNECTIONS ri Xi V Thrashing:; giving signals to the equipotential buses 32, 34, 39, 40, the excitation signals Xi from the inverse outputs of those flip-flops 13 that are in the state "O, through the discharge valves 12 and the bit

the OR 11 elements are fed to the inputs of the read out shaper 10. At the same time, the address OR of the read out driver is excited through the control element OR 23 and the address gate 28

30 of that numeric ruler, the trigger of which the indication of 27 is in the state "I.

Under the action of bit and address half reads, the cores 3 of those bits in which () go into the "O" state, and the cores of the bits in which (i.e., Xi 0) remain in their original state. Thus, under the action of the bit and address half-currents of reading, the cores of each bit of the selected numerical range take the state corresponding to the result of the logical conjunction / Vg operation. At the same time, on each read bit of the reading, a signal appears corresponding to the logical interdiction operation performed in this bit. These signals are fed to the inputs of the read amplifiers 20 and, if there is a control signal, the bus 40 is removed from the output gates 21. At the same time, the signals from the amplifiers 20 are sent to the delay elements 17, where they are delayed and then fed through the open gates 16 of the single trigger input of the word to the single trigger input 13 of word register 14. Output 19 through the output valves 18 is the result of a logic function

Gg Hg / yi.

All other logical operations listed in the table are performed in the same way.

As can be seen from the table in the proposed logical memory it is possible to perform logical conjunction operations,

disjunctions of pr Ug, Implications Pi

 and prohibition with obtaining the result directly in the selected numerical line 2, as well as operations of conjunction, prohibition, prohibition

 and Pierce arrows dg Xg1rg with the result at outputs 22 at the moment of performing operations when a signal is sent to control panel 40. In addition, when signals are sent to the corresponding control areas 31-39, you can get the results of fourteen logical operations: conjunction Gg L: g / U , CONVENTIONS Gg Ug, Prohibition Gg l; gLg / g; prohibition of implication Gg X {t / g; IMPLICATIONS Gg Ug Hg.,

Pierce arrow arrows Schaeffer

ri Xilyi r, - -r / i; P yr; g, - 0 at the outputs of 19.

Subject invention

Logical memory device containing a drive with numerical rulers on toroidal cores with a hysteresis square loop stitched by address write and read buses and bit write, read and read buses, connected respectively to address and bit write and read chips , word register, reading amplifiers, address and bit valves and "OR" elements, characterized in that, in order to expand the functionality, each bit, devices with holds a delay element, two output valves, and two zero and single-input valves of the word trigger, the output of the reading amplifier is connected to the input of the delay element, the output of the delay element is connected to the single and zero valves of the word trigger, and the output of the word trigger through the output valves output terminals of the device.

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