SU1721835A1 - Frame synchronizer - Google Patents

Abstract

The invention relates to the transmission of discrete information. The purpose of the invention is to simplify the device. The device contains a shift register 1, a multiplexer 2, a comparison unit 3, a reference register 4, a channel polling unit 5, a control unit 6, a memory unit 7, and a counter 8. The device allows processing information from several devices on the same equipment sources organized according to the principle of bit time compaction, which leads to the achievement of the goal. 8 il.

Description

WITH

with

Xi

go

00 00

ate

The invention relates to the field of discrete information transfer, in particular, to synchronization devices for cycles and frames.

The purpose of the invention is to expand the functionality by processing multi-channel signals with temporary bit-wise multiplexing from several sources.

Figure 1 shows the structural diagram of the device; 2 shows the structure of the organization of the memory block; FIG. 3 is a diagram of the organization of the information accumulation matrix; figure 4 is a block diagram of the register of the standard; FIG. 5 shows an example of the implementation of a multiplexer and a program for controlling its operation; fig.b is a control block diagram; FIG. 7 is a timing diagram of control signals; FIG. 8 is a block diagram of a channel polling unit.

The table shows the program of the device.

The device contains a shift register 1, a multiplexer 2, a comparison unit 3, a reference register 4, a channel sampling unit 5, a control unit 6, a memory unit 7 and an 8-bit counter.

Multiplexer 2 contains bit switches 9. The control unit 6 blocks generator 10, counter 11, decoder 12, and element 13. Channel polling unit contains triggers 14 and 15, multiplexers 16 and 17, decoder 18, and shapers 19 short pulses.

The device polls the channel group and searches in each channel the sync pattern distributed in the stream of information bits. For each channel, the sync pattern can have its own value and size.

The device works as follows.

Before starting work, the initial installation of all blocks and elements of the device is performed. In memory block 7, the reference sync combinations and their lengths are recorded for all input channels in accordance with their number in the standard storage area. The chains for setting the initial conditions, synchronization, and entry of the tuning data are not shown.

Block 5 of the survey using the appropriate clock pulses produces beaten registration of input information on the trigger 15, independently for each channel.

The channel number received from control block 6 outputs block 5 with the registered value of the information bit and the Request signal, which is generated by the clock pulse that accompanies the information bit. The Request signal informs that the next information bit has been received at the device input via this channel,

The control unit 6 on each information processing cycle of one channel generates seven control pulses T1 ... T7 (Figures 2 and 8). At the beginning of the processing cycle, block 6 sets the next channel address. By

0, the control pulse T1 acting on the first output of block 6, register 4 sets the values of the reference sync combinations of the polled channel and its length, which are recorded in the storage area of this memory block 7. The length of register 4 is (P + A) - bit, where P is the maximum sync pattern bit width. and A is the number of bits into which the sync pattern line code is written.

0 At the same time, the number of the processed time interval from the corresponding area of the block is recorded in counter 8. 7 memories.

On the control pulse T2, from the storage area of the input information of the memory unit 7, information accumulated over the channel is read. The read information is entered in register 1, the width of which is equal to R. Older bits

The 0 addresses of the readable cell of the block 7 are specified by the channel address, and the lower ones by the counter 8. Thus, at the time T2,

reading the input information accumulated over a given channel for the corresponding

5 time interval. By time interval is meant the distance between the sync bits in the information sequence. The accumulation of information in the memory block is carried out in the form of

0 matrices, the row length of which is determined by the number of bits in the sync combinations, and the column length — the number of the time interval specified by the counter 8. Arranging the matrix to search for sync combinations for the length

5 P bits and the distance between sync bits (time interval) Q - bit is illustrated in Fig. 4.

On the control pulse TZ in the presence of a signal. The request from block 5 produces a shift of the contents of register 1 by one bit and writing into it the next input bit from the batch 5.

Multiplexer 2 connects to the inputs of block 3 a comparison of the number of bits

5 of register 1, which was specified by the tuning word written in the lower bits of the register of the standard 4. The reference sync combination enters the second group of inputs of block 3 from the high bits of register 4.

When a sync-combination is detected, unit 3 delivers a comparison pulse to the device output. The moment of selection of the search result is made on the basis of the Selection signal generated on the controlled pulse T4. T4 pulse formation is performed only if there is an enable signal. Request from block 5. The ownership of the search result is determined at the output of the device according to the channel number from the block b.

The next control pulse T5 at the address of the same channel writes to the storage area of the input information of the block

7 register content 1.

By control pulse T6 counter

8increases its contents by one. This means that if a bit of the 1st time interval was processed on this access cycle, then the next time you access this channel, the bit (1 +1) -th time interval will be processed.

On pulse T7, the contents of the time interval of block 7 are recorded in the storage area of the values of block 7.

Thus, the device accumulates input and service information of this channel.

Then block 6 changes the channel number and the program of the device operation (Fig. 2) repeats, but already with the data of the new channel.

In the case of the absence of a signal request, the operation of the device over the polled channel is reduced only to performing read and write operations, i.e. the device operates only on control pulses 1,2,5,7. This ensures that the accumulated data is saved.

To avoid the loss of incoming input information, the processing time of all channels, i.e. the formation of programs (figure 2) of the work of all channels must be less than the duration of the information bit of the most high-speed channel.

Thus, in the proposed device, multichannel signal processing with time bit compaction is carried out, and the input information flows can be of different speeds.

Fig. 3 shows the organization structure of memory block 7. The entire memory is divided into the following areas: the input information storage area (contents of register 1), the time interval storage area (contents of counter 8), and the standard storage area (reference sync pattern and its length, read into register 4). This information is divided the corresponding bitness, and the division of the channel information is given by the corresponding number

channel addressing. The standard storage area is used only in the read mode, the remaining areas of the storage unit are also used in the write mode under the influence of the corresponding control pulses,

0 and for simplicity, it is assumed that the memory unit in the absence of write pulses is constantly in read mode. Figure 4 illustrates the division of the information flow Bit 1 into time intervals, as well as the construction of the accumulation matrix of the input information.

The length of the time interval in this example is O. Each input information bit using counter 8

0 is assigned the corresponding number from 1 to Q. So, at this stage of processing, the received bit is assigned the number 1 (the BP bit, the next time the channel is accessed

5, number 2 (a) and it will be placed in the second address cell, etc.

After the device has viewed the entire time interval of this channel, counter 8 will be reset and the process

0 repeat The use of a shift register 1 allows all incoming information to be accumulated in a memory block. Thus, in the matrix, the accumulation of information decomposed by

5 of its belonging to the positions (numbers) of the time interval, i.e. in one cell there will be information belonging to position ai, in the other address cell - INFORMATION POSITION 32, AND B

0 the corresponding address cell is a synchronization combination that is detected by comparing the contents of each address cell with a reference.

Multiplexer 2 implementation example

5 is shown in FIG. 2b, and FIG. Bb is a program for controlling its operation for four bits. The length in Fig. Bb refers to the number of data bits passed by the multiplexer.

0 2 to block 3 comparisons. The remaining bits will be represented by logical zeroes.

The control unit 6 consists of the generator 10, the counter 11, the decoder 12 and the element And 13. The output of the lower bits

5, the counter 11 is fed to the decoder 12, the outputs of which generate control pulses, and the outputs of the higher bits of the counter 11 set the channel number. The control pulse (T4) and the signal. The request from the output of the channel polling unit 5 is fed to the corresponding inputs of the AND element 13, the output of which is the fourth output of the block 6 and the output of the device selection signal.

Figure 9 presents the block diagram of the block 5 of the survey channels. It consists of clock triggers 14, information triggers 15, multiplexers 16 and 17, decoder 18 and shapers 19 short pulse. On the front of the accompanying clock pulse (Fig. 86), the trigger 14 of this channel is set to the log state. 1. The output of this trigger on a clock input controls the trigger 15 of the same channel. On the signal front at the C input, trigger 15 senses the value of the input information bit. By the addressable channel, multiplexers 16 and 17 switch the outputs of the corresponding triggers to the outputs of block 5. The presence of a signal. The request (trigger 14 on the polled channel is triggered by the received clock pulse) indicates that the device requires information to be processed on this channel. The resetting of the flip-flops 14 and 15 of each channel is performed when the transition to the next channel is triggered by a signal from the output of the decoder 18, shortened by the corresponding driver 19.

When compared with the known, the proposed device allows the same equipment to process information from several sources organized according to the principle of bit time multiplexing, which leads to a decrease in hardware costs.

Invention Formula

A frame alignment device containing serially connected shift register and memory block, serially connected reference register and comparison unit, as well as a multiplexer, a counter

room

control pulse

Reading from block 7 to register 4 and counter 8

Reading from block 7 to register 1

Shift information in the register 1

Selection of the comparison result

Write the contents of register 1 in block 7

Add 1 to the contents of the counter 8

Write the contents of counter 8 in block 7

bit and control unit, characterized in that, in order to expand the functionality by processing multi-channel signals with time-based multiplexing coming from several sources, a channel polling unit is inserted, while the information output of the channel polling unit is connected to the information input of the shift register, which controls the input of which is connected to the output of the request signal of the channel polling unit, to the input of the control unit and to the enable input of the bit counter, the outputs of which are connected to the address inputs of the memory block and, to the signal input, whose channel number and to the signal input, the channel number of the channel polling unit is connected to the corresponding output of the control unit, the first control output of which is connected to the control inputs of parallel recording of the bit counter and the reference register, the other outputs of which are connected to the control inputs of the multiplexer , to the inputs of which the outputs of the shift register are connected, and the outputs of the multiplexer are connected to other inputs of the comparison unit, the outputs of the memory unit are connected to the inputs of the parallel information of the register Etal it, the shift register and the bit counter, to the counting input of which the corresponding output of the control unit is connected, the other outputs of which are connected respectively to the first and second recording control write inputs of the memory block and to the control input of the parallel recording and to the shift control input of the shift register, and the information inputs and clock inputs of the polling unit channels and the output of the comparison unit are respectively the information, clock inputs and output of the device, the outputs of which the Channel Number and the Information Selection are the corresponding outputs of the control unit.

Perform operations

From block

Temporary

room

temporary

interbaAO.

one

;; :/::;to;

L

 i

but

FIG. 2

g

KblokamSchiv

The length of the greatest shnhrokombinatsii.

41 II

 H

eleven

3

To 5lok J To block

J

™ 1

/ MVU T T

1Sli From block 7

Wg

Fy

but

Xj

ABOUT

n

MX 9.1

Ґ2

 52

Have

yj

7

From block 5

™ 1

OTP

X2

x;

.From block 4

l

Jt

well

 // x 5J

W

 A4

W

P

//

t.5

77

eleven

tb

L

/ J

FIG. 6

Claims (1)

The claims ⁴ A cyclic synchronization device comprising a shift register and a memory unit connected in series, a reference register and a comparison unit connected in series, as well as a multiplexer, a bit counter and a control unit, characterized in that, in order to expand the functionality by processing multi-channel signals with a temporary 5-bit compression coming from several sources, a channel polling unit is introduced, while the information output of the channel polling unit is connected to the information input of the shift register the input 10 of which is connected to the output of the request signal of the channel polling unit, with the input of the control unit and with the enable input of the bit counter, the outputs of which are connected to the address inputs of the memory block, to input 15 of the signal Channel number ”of which and to the signal input Channel number of the channel polling unit the corresponding output of the control unit is connected, the first control output of which is connected to the control inputs 20 of the parallel recording of the bit counter and the standard register, the other outputs of which are connected to the control inputs of the multiplexer, the inputs of which are connected to the outputs of the shift register, and the outputs of the multi25 plexer are connected to other inputs of the comparison unit, the outputs of the memory unit are connected to the inputs of the parallel information of the standard register, shift register and bit counter, to the counting input of which there are 30 keys the corresponding output of the control unit, the other outputs of which are connected respectively, with the first and second control inputs of the memory block record and with the control input of the parallel record 35 and with the control input of the shift register shift, and the information inputs s and clock inputs of the block polling and the output channels are respectively unit comparison information, clock input 40 and the output device outputs a channel selection number and information which are respective outputs of the control unit. Control pulse number Operation in progress T1 Reading from block 7 to register 4 and counter 8 T2 Reading from block 7 to register 1 TK Shift information in register 1 T4 Selection of a comparison result T5 Writing the contents of register 1 to block 7 Tb Addition 1 to the contents of the counter 8 T7 Writing the contents of counter 8 to block 7 From block 1 Storage Area Input ~~ Information Tj Zk_1_ Region Stored Reference Storage Area Synchro Length combination ·. From block b ' Ί * From block a Time span N-1> <------ Uj ι Time interval No.Z room Time interval To blocks Vt, and 8 Length of greatest g 7 synchro combination 1 a? a? - 2 1 ........ a 'o / - of 1 t a- af - - > ci - - Fig.Z To block 3 To block 2 Length 0 0 1 1 0 2 0 1 3 1 1 4 FIG. 6 //// 0. Tact Exercise! -J ----, ~ t -— g —η p ud.iot gg π p Yp.imp.tZ _n Otp. TsprimptZ 1___________ 1 ______ g Tspr.imptb Resp. 7- .. P FIG. 8