SU1104679A1 - Cycle phasing device for digital information transmission equipment - Google Patents

Abstract

A CYCLE PHASE DEVICE OF DISCRETE INFORMATION TRANSMISSION EQUIPMENT containing a register comparison unit and a decision block whose output is an output of a cycle phasing device of discrete information transmission equipment, characterized in that, with the aim of expanding the functionality by providing work with a different sync structure, , a serially connected spreader and a switch, a serially connected 1e control unit and an adder, and also about An operational storage unit whose output is connected to the first input of the comparison unit, the second input of which is connected to the second output of the control unit, and the output of the comparison unit is connected to the information input of the decision unit, the installation input of which is connected to the third output of the control unit, the fourth output of which is connected to the installation input of the distributor, the output of the register is connected to the address input of the operational storage unit and to the second input of the adder, the output of which is connected to the second input for a switch whose output is connected to the information input of the register, the second input of the distributor is combined with the reset input of the decision unit and is the first clock input of the cyclic phasing device of the discrete information transmission equipment, the second clock input of which is the combined clock inputs of the control unit, register and real-time storage unit and the control input of the control unit, the information input of the operative memory. unit, as well as the combined write / read inputs of the switch and the random access memory block are (respectively) the input control, the information input and the write / read input of the cyclic phasing device of the transmission equipment from the discrete information. 2. POP.1 device, different the fact that the distributor contains a serially connected frequency divider and a reference element, the output of which is connected to the installation input of the frequency divider, the second input of the element is equal to vl nor, the counting input is deli The frequencies about and the output of the frequency divider are the first and second inputs and output of the distributor, respectively. 3. The device according to claim 1, which is that the control unit contains a memory register of the number of bits in the cycle, memory register sync bin, the memory register of the number of bits of information between adjacent bits of the sync combination and the memory register of the number of bits in the sync combination,

Description

The input inputs of which are the control input of the control unit, the clock input of the synchronization memory register are the clock input of the control unit, and the outputs of the memory register of the number of information bits between adjacent bits of the sync combination.

the sync memory register, the number of bits in the sync combination register, and the number of bits in a cycle memory register are the first, second, third, and fourth outputs of the control unit, respectively.

one

The invention relates to telecommunications and can be used to cycle phasing of discrete information transmission systems.

A cyclic phasing device is known that contains a key connected in series, a shift register, a decoder, the first and second elements AND, a comparison block connected in series, a match number counter and a trigger, a serially connected decoder and a memory block whose output is connected to the second input of the second element I, the output of the first element - And connected to the input of the key and the second installation input of the trigger, the second input of the key is connected to the output of the counter of the number of matches, the second output of the shift register is connected to retemu entry key entry and comparison unit, the fourth input key is combined with a second input of the comparison unit and the input of the decoder, and a trigger output connected to a second input of the first AND A.

A disadvantage of the prior art cyclic phasing apparatus is the lack of cyclic phasing capability with a different structure of a cyclic oscillator of the received signal.

The closest technical solution to the expected one is the cyclic phasing device of the discrete information transmission equipment, which contains the register, the AND comparison unit, the decisive unit whose output is the output of the cyclic phasing device of the discrete information transmission equipment, successively connected strobe unit and the correction unit, and also the counter whose input and output are connected respectively to the output of the comparison unit and the input of the counter, the output of which is connected to the input of the decision unit, the first, The second and third outputs of the register are connected to the corresponding combined inputs of the correction unit and the comparison unit, the first, second and third outputs of which are connected to the corresponding inputs of the register, and the rise of the correction unit is connected to the input of the comparison unit 2.

A disadvantage of the known device for cyclic phasing of the equipment for transmitting discrete information is the absence of the possibility of cyclic phasing with a different sync cycle structure of the received signal.

The purpose of the invention is the expansion of functional capabilities by providing cyclic phasing with a different structure of the sync cycle of the received signal.

In order to achieve this goal, the serially connected distributor and switch, the serially connected control unit and the sum are entered into the cyclic phasing device of the discrete information transmission equipment containing the register, the comparison unit and the decisive unit whose output is the output of the cyclic phasing device of the discrete information transmission equipment. A torus as well as an operational storage unit, the output of which is connected to the first input of the comparison unit, the second input of which is connected to the second stage of the control unit, and the output of the comparison unit is connected to the information input of the decision unit, the installation input of which is connected to the third input of the control unit. the fourth output of which is connected to the installation input of the distributor; the register output is connected to the address input of the operational storage unit and to the second input of the adder, the output of which is connected to the second input of the switch, the output of which is connected to the information input of the register; the second input of the distributor is combined with the reset input of the decision unit and is the first clock input of the cyclic phasing device of the discrete information transmission equipment, the second clock input of which is the combined The control inputs of the control unit, the register and the operational storage unit, and the control input of the control unit, the information input of the operational storage unit, and the same combined write / read inputs of the switch and the operational storage unit are respectively the control input, the information input and Record input / SCR device cyclic phasing of the equipment for transmitting discrete information. The distributor comprises a serially connected frequency divider and a reference element, the output of which is connected to the installation input of the frequency divider, the second input of the comparison element, the counting input of the frequency divider and the output of the frequency divider are respectively the first and second inputs and the output of the distributor. The control unit contains the memory register of the number of bits in the cycle, the memory register of the sync combination, the memory register of the number of bits of information between adjacent bits of the sync combination and the memory register of the number of bits in the sync bit, the combined inputs of which are the control input of the register the memory of the sync pattern is the same as the input of the control unit, and the outputs of the memory register of the number of information bits between adjacent bits of the sync combination, the memory register of the sync combination, of the memory register of the number of bits in sync and combinations of register memory the number of bits in the cycle are respectively perpym, second, third and fourth outputs them to the control unit. FIG. 1 shows the structural electrical circuit of the device for cyclic phasing of discrete information transmission equipment; FIG. 2 shows signal diagrams explaining its operation. The cyclic phasing device for the discrete information transmission equipment contains the distributor 1, the switch 2, the register 3, the operational storage unit 4, the comparison unit 5, the decisive unit 6, the adder 7 and the etching unit 8. Distributor 1 contains frequency divider 9 and reference element 10. The control unit 8 contains a memory register 11 of the number of bits in the cycle, a memory register 12 of the sync pattern, a memory register 13 of the number of information bits between adjacent bits of the sync combination, a register 14 of the number of bits in the sync combination. Solving unit 6 contains a counter 15 and a comparison element 16. The device for cyclic phasing of the discrete i-transmission equipment operates as follows. Each cycle of the received signal contains N bits, of which the bits belong to the sync pattern bits that are uniformly located in the cycle. The number of bits of information between any adjacent bits of the sync pattern is equal to g bits. These data, which determine the structure of the sync cycle of the received signal before starting work, are recorded through the control input to control unit 8 (Fig. 1) B. The register 11 is written in binary code number N. In register 12, a sync pattern for the particular received signal is written. In register 13, the number r is written in the same code. In register 14, the number B is written in binary code. The received signal (Fig. 2a) is fed to the information input of the operative memory unit 4, which by the write / read signal (Fig 2d), arriving at the write / read input of the cyclic phasing device of the discrete information transmission equipment, is transferred to the write mode. Clock pulses of frequency Fj- (fig. 26) are fed through the second input of the distributor 1 to the counting input of the divider 9. To the second input of the comparison element 10, the binary code N, 5 1 specifies the division factor of divider 9 coming from the register 11 of the control unit 8 in binary code. At the first input of the comparison element 10 signals are received from 9. If the binary numbers on the first and second inputs of the comparison element 10 are equal, it outputs a pulse at its output, setting the divider 9 in O. Thus, you can set the required divider division ratio 9. Signals from the output of the divider 9 through the switch 2, controlled by the write / read signal (Fig. 2e) at the time of recording (a high level of the specified signal) is fed to the input of the register 3 and is stored in it in time with the first pulse F (Fig. 2e). The clock pulses 7, the frequency of which is F, are fed to the cyclic phase-out device of the Baffle apparatus for transmitting discrete information via the second clock input. Signals from the output of register 3 are sent to the address inputs of the operational storage unit 4. Thus, in the write mode, the addresses of the operational storage unit 4 are determined by the state of the distributor 1 (Fig. 2b). After recording the information, the operational storage unit 4 is transferred to the mode (Fig. 2e). ) read (low level of the write signal) and reads information from the operational storage unit 4 with each clock frequency F, while the addresses of the operational storage unit 4 (Fig. 2d) are formed as follows. Let the recording of information take place at address t. Register 3 remembered the number t. The first read cycle also occurs at address ha. In the next read cycle, the inputs to the register 3 receive signals from the output of the adder 7, since the switch 2 is switched by the write / read signal. The second input of the adder 7 receives signals from the output of register 3 (the number m in the binary code), the first input of the adder 7 receives signals (the number r in the binary code) from the output of the register 13 of the control unit-8. At the output of the adder 7, the number mr is generated in the binary code, which is stored in register 3. In the next cycle F, the second input of the adder 7 is received by mr, and the first input is again r and in the register 3 the number m-2r and t .d In the next cycle F, information will be recorded at address t + 1, the first read cycle at ra + 1-r, the second read cycle at m + 1-2r, etc. (Fig. 2d). The read from the operative storage unit 4 of information (Fig. 2g) is fed to the input of a one-bit comparison unit 5, to the second input of which is in tact with the read information, i.e. In time with each clock pulse F, the synchrocombinade and standard (Fig. 2h) is outputted from the output of the register 12 of the control unit 8. When a bit read from the operational storage unit 4 and the sync pattern bit received from the output of register 12 coincides, a pulse is formed at the output of comparison unit 5 (FIG. 2i), of inputs to the input of counter 15 of the decision block 6, Counter 15 counts the pulses arriving at its input is for cycle F, after which it is reset to O by pulses F. The signals from the output of counter 15 are fed to the input of the reference element 16, to another input of which in binary code the number E is from the output of pe-. Gistra 14 control block 8. If the counter 15 counts for hshkl F-j. 6 pulses, then at the output of the comparison element 16 a pulse is formed (Fig. 2k) arriving at the trimming of the receiving part of the apparatus. Thus, in the proposed device, the operation is provided with a different structure of the clock cycle of the received signal.

Yes

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Claims (3)

A CYCLE PHASING DEVICE FOR DISCRETE INFORMATION TRANSMISSION DEVICES, comprising a register> a comparison unit and a deciding unit, the output of which is an output of a cyclic phasing device for transmitting discrete information, characterized in that, in order to expand the functionality by providing operation with a different structure of the received signal clock, a distributor and a switch are connected in series, a control unit and an adder are connected in series, and an operative the second storage unit, the output of which is connected to the first input of the comparison unit, the second input of which is connected to the second output of the control unit, and the output of the comparison unit is connected to the information input of the deciding unit, the installation input of which is connected to the third output of the control unit, the fourth output of which is connected to the installation input of the distributor, the output of the register is connected to the address input of the random access memory and to the second input of the adder, the output of which is connected to the second input of the switch, the output of which is connected to the information input of the register, the second input of the distributor is combined with the reset input of the decision block and is the first clock input of the device for cyclic phasing of discrete information transmission equipment, the second clock input of which is the combined clock inputs of the control unit, register and random access memory, and the control control unit input, operational memory input. unit, as well as the combined recording / reading inputs of the switch and random access memory are respectively the control input, information input and write / read input of the phasing device for discrete information transmission equipment. 2. The device according to claim 1, characterized in that the distributor contains a series-connected frequency divider and a comparison element, the output of which is connected to the installation input of the frequency divider, the second input of the comparison element, the counted input of the frequency divider and the output of the frequency divider are respectively the first and second inputs and the output of the dispenser. 3. The device according to claim 1, wherein the control unit comprises a memory register of the number of bits in the cycle, a memory register of the sync combination, a memory register of the number of bits of information between adjacent bits of the sync combination, and a memory register of the number of bits in the sync combination , volume su _nu 1104679 1 104679 the cenical inputs of which are the control input of the control unit, the clock input of the synchronization memory register is the clock input of the control unit, and the outputs of the memory register of the number of information bits between adjacent bits of the sync combination, the memory register of the sync combination, the memory register of the number of bits in the sync combination and the memory register of the number of bits in the cycle are respectively the first, second, third and fourth outputs of the control unit.