SU1432796A1 - Device for retrieving noise-like signals - Google Patents

Abstract

FIELD OF THE INVENTION The invention relates to telecommunications and radar. The purpose of the invention is to improve noise immunity and reduce the search time for a noise-like signal. . The device contains limiter 1 level, delay line 2, multipliers 3, 4, adder 5, low-pass filter 6, controlled clock generator 7, keys 15, 8. shift register 9, adders 10, 11 modulo two, decoder 13, inverter 16, pulse counter 18. The goal is achieved by introducing an AND 19 element, an OR 20 element, a reversible counter 17 and an AND 21 element, as well as an RS flip-flop 14 and a block of adders 12 into the device. 1 Il.

Description

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The invention relates to telecommunications and radar and can be used to search and synchronize noise-like signals.

The purpose of the invention is to improve noise immunity and reduce the search time for a noise-like signal.

The drawing shows a structural electrical circuit of the tO device for searching for noise-like signals.

The device contains a limiter 1 level, delay line 2, the first and second multipliers 3 and 4, the adder 5, the low-pass filter 6, the control clock generator 7, the second key 8, the shift register 9, the first and second adders 10 and 11 modulo; two, block 12 adders, decoder

13, RS flip-flop 14, first key 15, 20: inverter 16, reversible counter 17, pulse counter 18, first element I AND 19, element OR 20, second element I And 21.

I The device works as follows: 25 I time.

I In the initial state of the device: search for noise-like signals of the reverse; Common counter 17, counter 18 and re-; the shift 9 is reset, and the RS-flip-flop: 14 is set in such a state that the first key 15 is closed and connects the first input of the second key 8 to its output. When the input signal of a noise-like signal, / (PSS) input signal arrives, register 9 begins to fill through limiter 1 and the second key 8. Filling occurs in such a way that the first discharge (1 p) of register 9 will record 0: (2 p) -th element of the input (binary) signal, in the second (2 p) - (2n-1) -th element, etc., and in 2p bit (2pr) - the first element. After register 9 is filled up in block 12, the sumps of the first n elements written in (n + 1) - 2p bits are formed, according to a given polynomial, n + 1, n + 2, 2n, pseudo-random binary signal elements, which -D are compared with similar elements coming from bits 1p - pr register 9.

If all 2p elements recorded in register 9 do not have errors, all outputs of block 12 adders appear to be zeros. This state is determined by the decoder 13, which by its output pulse switches the RS flip-flop 14. The latter opens the first key 13 and switches the second key 8, as a result of which the output of the first adder 10 is connected to the information input of the register 9, and to the second information input of the reversible counter 17 receive clock pulses.

When the feedback of register 9 is closed in bits 1p, a pseudo-random sequence is generated, the elements of which are compared with elements of the input signal in the second adder 11, from the output of which the signal goes to the reversible counter 17 to control the counting direction. At the same time, liB counts clock pulses. When it reaches the value of N (the NSS length), i.e. when the internal oscillator, formed by the register 9 and the first adder 10, has formed the entire period of the PSS, at the input of the counter 18 there is also a poll of poll.

Depending on whether the reversible counter counted 17 number sov-. drops of elements of the input binary signal with elements of the internal 1ShTS up to a certain threshold, at its output will be either O or 1. If the threshold is exceeded, then the signal 1c from the output of the reversible counter 17 and the polling pulse from the output of counter 18, arriving at the second element I 21 , a sync pulse is formed at its output, which arrives at the output of the noise-like signal searching device and, through the first element OR 20, sets in О a reversible counter 17, preparing the noise-like signal searching device for further work. If the threshold is not reached, then O at the output of the reversible counter 17 through the inverter 16 is fed to the first element AND 19. When a polling pulse arrives at the first element And 19, a pulse appears at its output that switches the RS flip-flop 14 and through the element OR 20 resets the reversible counter 17. The second key 8 again connects the output of the limiter 1 to the information input of the register 9, which begins to be filled with elements of the binary signal, i, e. the whole process is repeated. The same happens in the case when, at the output of block 12, the sum of maters does not appear at all outputs

Oh i segment 1) AL recorded in register 9 has errors.

In this case, a search is carried out in the PSS of a segment of length 2p, without errors in the elements, and then a check is made for the establishment of synchronization.

After filling the register 9, the delay tracking unit, consisting of the first and second multipliers 3 and 4, the adder 5, the filter 6 and the register 9, captures the signal. The first and second multipliers 3 and 4 multiply the input signal from the delay line 2 by the signal from the outputs of two different bits of register 9, and the result is summed in adder 5 and filtered in the filter. As a result, the clock error signal is generated, the input of the controlled clock generator 7 and changes the frequency of the repetition of clock pulses.

Claims (1)

Invention Formula A device for searching noise-like signals containing subsequently connected level limiter, delay line, first multiplier adder, low pass filter, controlled clock generator, first key, pulse counter, serially connected second key, shift register, first modulo two and second modulo two, the second input of which is connected to the first information input of the second key, as well as the decoder, inverter and second multiplier, the first and second inputs of which are connected The output of the delay line and the perrom output is transferred by the output of the device. ra sd1ziga, the second exit Transfer. the shift register is connected to the second input of the first multiplier, the output of which is connected to the second input of the adder, and the output of the first modulo-two adder is connected to the second information input of the second key, and the input of the level limiter is an input of the device, in order to improve noise immunity and reduce the search time of the noise-like signal, entered in series The first element is And, the element I.PI, the reversible counter and the second element And, the second input of which is connected to the first input ifepBoro of the element And and the output of the pulse counter, as well as the RS trigger and block adders, while the inputs of the block adders are connected to the corresponding outputs of the register bits shift, the outputs of the block adders are connected to the corresponding to the inputs of the decoder, the output of which is connected via RS-trigger to the control inputs of the first key and second key, the first information input of which is connected to the output of the level limiter 1-1, the output of the second modulo-two adder is connected to the first information input of the reversible counter, the output of which is the inverter is connected to the second input the first element And, the second information input of the reversible counter is connected to the output of the first key, the outputs of the first and second elements And are connected respectively to the S-input. RS-flip-flop and the second input of the OR element, and the second input of the first modulo adder. two are connected to the corresponding ry output of the shift register, and the output of the second element