RU1829122C - Device of phase start of recurrent sequence - Google Patents

Abstract

The invention relates to communication technology and can be used to increase the likelihood of a phase start of a recurrence sequence. The purpose of the invention is to increase the likelihood of receiving a phase start of a recurrence sequence. The phase start device of a recurrence sequence contains a first mode switch 1, a recursive register, an adder 3 modulo two, a decoder 4, a second mode switch 5, a shift register 6. threshold block 7. OR element 8, AND elements 9, 10 and 11, pulse counter 12, AND element 13 and delay element 14. 1 ill.

Description

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The invention relates to communication technology and can be used to increase the likelihood of a phase start of a recurrence sequence.

The purpose of the invention is to increase the likelihood of a phase start of a recurrence sequence.

The proposed device for phase triggering a recurrence sequence has significant features that distinguish it from the prototype both in terms of the composition of the elements - this is the second mode switch, the third and fourth elements And, the delay element, the shift register, and the connections between the elements, which provides a positive effect which consists in increasing the likelihood of a phase start of the recurrence sequence. The introduced set of new features allows eliminating the disadvantages inherent in the known device.

The drawing shows a phase trigger device recurrence sequence.

The recursion sequence phase start device comprises a switch 1 of operating modes with two information inputs and an information output, four control inputs and two control outputs, a recursive shift register 2 by n bits, an adder 3 modulo 2, a decoder 4, a switch 5 of operating modes with two information inputs and two information outputs, three control inputs and two control outputs, shift register 6 by (k + N) bits with information input, output and output with a bit to, the input of the clock (shear) frequency, the threshold block 7, the element OR 8, the elements 9, 10 and 11., the counter 12 with the volume of the account (k + N) and an additional output with bit k, element And 13, delay element 14, the second input of the OR element 8 is the input of the clock frequency F, the second input of the element AND 13 is the input of the high clock frequency m, with f (k + N) F, the inputs of the Reset pulse counters, shift register and threshold element and the fourth control input of the first mode switch and the first control input of the second mode switch interconnected and are the input of the Reset signal. In this device, the RP is considered highlighted (received) if there are less than m errors in a section of N bits received from the channel, followed by k undistorted bits, and the feedback of the receiver recurrence register 2 is closed to

undistorted plot. Checking the presence of these criteria in the received sequence is carried out with the reception of each bit, for which purpose

accumulation on the shift register 6 of the comparison signals from the adder 3 with a volume of (k + N) bits and analysis for the presence of both criteria in them. The analysis is carried out with a high frequency f (k + N), which allows it to be performed in

frequency beat F.

The proposed device operates as follows:

Before starting work with a signal on the Reset circuit, the elements of the device are set to their initial state, while

- the passage of information signals arriving at the first information input of switch 1 is allowed, through its information output to the input of register 2;

- from the second control output of switch 1, a inhibit signal is supplied to the second input of AND element 10;

-threshold block 7 and counter 12 are set to zero;

the elements of the shift register 6 are set to

- at the first control input of switch 5, a signal is set allowing the passage of signals from the output of adder 3 to the input of register 6.

The binary signs of the recurrence sequence received from the communication channel with frequency P, through the switch 1, are fed to the input of the recurrence register of shift 2, the feedback of which is open. The sequence obtained at the output of register 2 is compared by adder 3 with the input sequence. At

Moreover, if the signs of the recurrence sequence coming from the communication channel are not distorted, then a sequence of zeros will come from the output of adder 3. In case of interference in the communication channel from the output of the adder

3, along with zeros (signs of comparison), units (incomparable signals) will also arrive. This sequence of comparison signals and non-comparison signals with each bit of information coming

from the communication channel, through the switch 5 it is fed to the input of the shift register b, which through (k + N) clocks will be filled with them.

After each entry in the shift register b signal from the adder 3 the contents of the register

b is analyzed for compliance with the criteria for the selection of RP. To this end, the presence or absence of errors in the first k characters of the shift register 6 is determined and the number of incomparable characters found throughout the shift register b (actually in the last N characters of it) is counted. The absence of errors in the first k characters of register 6 indicates that the recurrent register 2 is currently filled with distorted RP signs, and the presence in register 6 of the number of errors is less than m that the channel actually receives RP.

Said checks are performed as follows.

With the arrival of the pulse of the clock frequency F at the output of the element OR 8 at the second input of the element И И I. 8, the signal arrives at the clock input of the register 6, the signal from the output of the adder 3 is recorded in the first bit of the register 6, and the contents of the register 6 are shifted by one bit. At the same time, the frequency signal F is input to the delay element 14. A pass delay element 14, the signal from its output is fed to the third control input of switch 5 and to the third control input of switch 1, while the feedback of register 6 is closed. with ne the control output of the switch 1 to the second input of the element And 9 receives an enable signal, from the first control output of the switch 5 to the first input of the element 11 receives the enable signal, from the second control output of the switch 5 to the second input of the element And 13 receives the enable signal, when this, through element And 13, a high frequency f goes to the input of counter 12, and through element OR 8 it goes to the clock (shift) input of register 6, Counter 12 starts counting the pulses received at its input, and the contents of register 6 and starts to be shifted, the signals from its output through the switch 5 receives at its input and a threshold input of the block 7.

If in the first k bits of register 6 there were signs of incomparability (errors), then through the open element And 11 they go to the second control input of the first switch, and from the first control output of the switch 1 to the first input of the element And 9 the receipt of the enabling signal, which will indicate the presence of errors in the first k characters of register 6 and the characters filling register 2, i.e. the first reception criterion for RP is not satisfied. If there are no incomparable signals in the first k characters of register 6, then no error signals are received at the second control input of the first switch and the enable signal will continue to be received at the first input of the And 9 element from the first control output of switch 1.

After k clock cycles of the device, at the output k of counter 12, a signal appears which is fed to the second control input of switch 5, while the first signal 5 of the control output of switch 5 receives the enable signal, which was received at the first input of AND 11 and subsequent k ticks insignificance letters from register b through element AND 11 not

0 will be supplied to the second control input of switch 1, which will ensure that the permission signal from the first control output of switch-tel 1 of the characters between the discharge

5 k and the end of the register 6 (volume N characters).

Signs of incomparability advancing through the register are received at the second information input of the bis switch of the second information output of the switch 5

0 go to the input of the register 6 and to the input of the threshold block 7, which calculates them. After (k + N) clock cycles of the device, a signal appears at the output of counter 12, which arrives at the first

5, the control input of switch 5, the feedback of the register b opens, and its state will be the same as before the feedback was closed (writing the last character from the adder 3 into it). Signal with

0 of counter 12 also polls the state of threshold block 7. If the number of incomparities in register 6 was greater than the specified hl, then after (k + N) cycles there is no signal at the output of threshold block 7, and with the arrival of

5 of the next pulse of frequency F, the next signal from the adder 3 will be written into register b and the contents of register 6 will be analyzed again. If the number of non-comparisons is less than or equal to rn, then

0, the output of the threshold block 7 receives a signal that arrives at the second input of the element And 9. If the first input of the element And 9 receives the enable signal from the first control output of switch 1 (i.e.

5 in the first k bits of the register there are no incomparable signals - register 2 is filled with undistorted characters), then the output of element And 9 shows a signal that goes to the first control input of the switch, and through the second information input and the information output of switch 1 is closed the feedback of the recurrence register 2 and the register goes into offline mode.

5 I will form RP signs synchronous with the signs coming from the communication channel.

When a control appears on it: a combination at the input of decoder 4, a signal appears that, through an open element And 10, enters its output and

the device is reset. The signal from the output of the And 10 element can be used as a phase start signal for discrete information transmission equipment.

SUMMARY OF THE INVENTION A phase start device for a recurrence sequence, comprising a first operating mode switch, a recurrence register, a decoder and a first AND element, as well as a pulse counter, an OR element, a threshold unit and a second AND element, the first input of which is connected to the first control output the first mode switch, the first information input of which is connected to the first input of the adder modulo two, the second input of which and the second information input of the first switch l operation mode are connected to the information output of the recurrence register, characterized in that, in order to increase the probability of receiving a phase start of the recursion sequence, a second operation mode switch, a third and fourth AND element, a delay element and a shift register are introduced into it, the second input atom the first element And is connected to the second control output of the first mode switch, the output of the threshold block through the second element And is connected to the first control input of the first mode switch, the adder output modulo two through the second mode switch is connected to the input of the shift register, the output of which is connected to another

the information input of the second mode switch, the second information output of which is connected to the input of the threshold block, the k-ro of the shift register bit is connected to the second control input of the first mode switch through the third AND element, the second input of which is connected to the first control output of the second

operating mode switch, the second control output of which is connected through the fourth AND element to the first input of the OR element and to the pulse counter input, the output of which is connected to the first control input of the second operating mode switch and with the input of the threshold block readout, k-ro output a pulse counter is connected to the second control input of the second switch

an operation mode, the third control input of which is connected to the output of the delay element and to the third control input of the first mode switch, the fourth control input of which is connected to the output of the first element And, the second input of the fourth element And is the input of a high-frequency signal, the second input of the OR element is connected to the input of the delay element and is an input

the clock signal, and the reset inputs of the pulse counter, shift register and threshold block, the fourth control input of the first mode switch and the first control input of the second mode switch are interconnected and are the input of the Reset signal,