SU1582344A1 - Digital discriminator of pulse frequency - Google Patents

Abstract

The invention relates to a pulse technique and can be used to select the minimum, average or maximum of three frequencies. The aim of the invention is to improve the selection accuracy by reducing the code change delay on the output buses when the input frequencies change. To achieve the goal, in the device containing channels 1–3, each of which includes a counter 4, triggers 6–9, counter 5, trigger 10, differential frequency selection block 11, shaper 12–14 pulses, blocks 15 are inserted into each channel. , 16 delays, registers 17, 18, reference element 19, AND elements 20–22, OR elements 23–27. Each channel 1–3 compares two of the three input frequencies. In the event that two pulses of another input frequency arrive between two pulses of one of the input frequencies, a pulse appears at one of the outputs of block 11 and a trigger 6 or trigger 9 is set. If the pulses at the inputs alternate, using the delay block 15, registers 17 and 18 and the comparison element 19 analyzes the change in the phase shift of these pulses, the sign of the increment of which depends on the sign of the frequency difference. This also sets one of the triggers 6, 9, 10. 2 Il.

Description

31582344

The invention relates to a pulse () technique and can be used to select a given frequency, both average and minimum or maximum, when working with frequency-pulse sensors.

The purpose of the invention is to improve the frequency selection accuracy by reducing the number of pulses of the input Q frequency, which elapses over the time counted from the moment when the current selected frequency has changed its value until the code changes at the output device. 15

FIG. 1 shows a block diagram of a digital pulse frequency discriminator; in fig. 2 - diagrams of its operation for one signal processing channel.

FIG. 2 The following notation is accepted: a - first entrance; b - the second input; c - the first output of the differential frequency selection block g - the second output of the differential difference selection block 25; d - the output of the second trigger; e - output of the third trigger; the magnitude of the shift; and - output A B of the comparison element j c - output A 3

- exit AB

- first exit second exit third exit

thirty

35

reference element; l comparison element, m channel (f f6); n - channel (fА fe); n - channel (fА f6).

The digital discriminator of the pulse frequency contains identical first second and third channels 1-3 of the signal processing, each of which contains the first and second counters 4 and 5 of the pulses, from the first to the fifth triggers 6-10, the differential frequency selection block 11, the first , second and third shapers 12-14 pulses, first and second blocks 15 and 16 delays, first and second registers 17 and 18, 45 comparison element 19, first, second and third elements AND 20-22, first to fifth elements OR as well as the first, second and third input buses 28 - 30, the first, second and third 5Q in Khodnev bus 31 33 of the first channel 1 signal processing, first, second and Toyota output bus 34 36 of the second channel signal processing 2, the first, second and third output buses 37 - 39 of the third channel 3 signal processing.

The first, second and third input tires 28 - 30 are connected respectively 55

Q 5

0

five

0

five

about 5 Q

five

but with the first inputs of blocks 11 of the first, second and third channels 1-3, moreover, (the first input bus 28 is connected to the second input of the block 11 of the second channel 2, the second input bus 29 is connected to the second input of the block 11 of the third channel 3, and the third input bus 30 - to the second input of block 11 of the first channel 1. In each channel, the first input of block 11 for separating the difference frequency is connected to the counting input of the first counter 4 and the input of the first driver 12. The second input of block 11 is connected to the counting input of the second counter 5 and the inputs of the second and third form Slaves 13 and 14. The first output of block 11 is connected to the S-input of the second trigger 7 and the first input of the first element OR 23, the output of which is connected to the S-input of the first trigger 6 and to the first inputs of the second and third elements OR 2k and 25. The second output unit 11 is connected to the S-input of the third trigger 8 and the first input of the fourth element OR 26, the output of the latter is connected to the S-input of the fourth trigger 9 to the second input of the third element OR 25 and the first input of the fifth element OR 27. The second inputs of the fourth and first elements OR 26 and 23 are connected respectively with in The outputs of the first and second elements And 20 and 21, the first inputs of which are connected to the outputs of the second and third triggers 7 and 8 and to the R inputs of the first and second counters 4 and 5, respectively, as well as to the first and second inputs of the third element And 22, output which is connected to the S-input of the fifth trigger 10 and the second inputs of the second and fifth elements OR 2k and 27. The output of the first shaper 12 is connected to the input of the first block 15, whose outputs are bitwise connected to the D-inputs of the first register 17 (the outputs of bitwise the bottom is connected to the D-inputs of the second regis Section 18 and to the first group of inputs of element 19, the second group of inputs of which is bitwise connected to the outputs of the second register 18. Output A of element 19 is connected to the second input of the first element I 20, output A B to the second input of the second element I 21. and output A B - with the third input of the third element And 22, the output of the third driver 14 is connected to the C-inputs

the second register 18. The output of the second block 16 is connected to the third inputs of the first and second elements And 20 and 21 and to the fourth input of the third element And 22. The outputs of the first and second counters k and 5 are connected to the C inputs of the second and third triggers 7 and 8, respectively . The outputs of the first, fourth and fifth of the triggers 6, 9 and 10 of the first channel 1 are connected to the first, second, third output buses, respectively, similarly the outputs of the second channel 2 are connected to buses 3–36, and the outputs of the third channel 3 are connected to buses. Output buses 31-39 are digital frequency discriminator outputs.

The magnitude of the delay of the first block 15 must not be less than the period following the input pulses. The number of outputs can be any, with their increase the accuracy of frequency comparison increases. The delay of the second block 16 must exceed the total delay introduced by the first and second registers 17 and 18 and element 19, but must be less than the length of the pause between the pulses of the input frequency. Delay blocks 15 and 16 can be implemented in any way, for example, on delay lines.

The unit 11 for generating differential frequency pulses must give out a pulse to its first output, if the frequency at its first input is lower than the frequency at its second input, if at the first input the frequency is higher, then the pulse must be given to the second output. As such a unit, you can use a known device.

The digital discriminator works as follows.

Before starting, the circuit is set to its original state, zeroed. In Fig 1, the reset circuit is conventionally not shown. The second and third triggers 7 and 8 are zeroed by applying a signal to the R input, and with their high potential from the inverse output they zero the first and second counters k and 5. To zero the first, fourth and fifth triggers 6, 9 and 10, you can use C input or send signals to R inputs via OR elements. After giving a signal Reset on all output tires set5823 nd

0

five

0

five

0

five

five

0

five

The potential is low.

Since the channel arrangement is the same, we consider the operation of one channel, for example, the first channel 1.

Input pulses from the input bus 28 and 30 are fed to the input unit 11 (Fig. 2A, b). Suppose there are two pulses on the input bus 30, and one on the input bus 28, then a pulse is generated at the first output of block 11 (Fig. 2c), which through the first OR element 23 arrives at the S input of the first trigger 6 and sets it to single state (fig. 2m), i.e. On the first output bus 31 of the first channel 1, a signal is generated that the frequency on the input bus 30 exceeds the frequency on the input bus 28. In addition, the pulse from the first output of the block 11 sets the second trigger 7 (1 d) to one state low potential from its inverse output closes the first and third elements associated with it AND 20 and 22, and also removes the reset from the first counter k. In the event of further arrival of pulses only to the input bus 3, the state of these elements does not change. If the pulses to the input buses 28 and 30 are received alternately, then the block 11 stops generating pulses at its output, the first counter k on the second pulse arriving at the input bus 28 after removing the reset, sets the second trigger 7 to zero (FIG. 2d). Since the pulse from the output of the counter enters the C input, trigger 7 is zeroed at the end. After the first trigger 7 is set to the initial state, the first and third elements AND 20 and 22 are opened at the first inputs.

Let us consider how the discriminator works when the input pulses are received alternately.

From the first input bus 28, a pulse through the first driver 12 is fed to the input of the first unit 15 and begins to advance along it. Since the delay value of the first block 15 is not less than the time between the input pulses, the pulse generated by the second driver 13 along the trailing edge of the pulse from the third input bus 30 enters the C-inputs of the first register 1; at TdKoe, the time when at some of the outputs of the first block 15 a signal is acquired, t, e, the mutual sending of pulses on the first and third input buses (Fig. 2g) is reflected in the code recorded in the first register 17. In the first register 17 each period, on the falling edge of the pulse from the third input bus 30, records the JQ code of the phase shift of the compared

frequencies. On the leading edge of the pulse of the third input bus 30, formed by the third driver Ik,

This code is rewritten into the second 55 register 18. Thus, the second register 18 stores the code fa

The reference shift of the compared frequencies of the previous period, and in the first register 17 of the current period. Element 2Q

19 compares the codes at the outputs of the first and second registers 17 and 18 and forms one of the three signals (Fig. 2i, k, l).

The signal A B is generated if the 25 code value in the first register 17 exceeds the code value in the second register 18 (Fig. 2l), the signal is if the code of the second register 18 is sick (Fig 2m), and the signal Ab in the ps-30 codes (FIG. 2n). The signals from the outputs of element 19 (Fig. 2i to l, l) are fed to elements 20-20, which are also associated with the outputs of the second 7 and third 8 flip-flops and the output of the second delay block 16 First, second and the third elements And 20 - 22 are open to the inputs connected to the outputs of the second and third triggers 7 and 8.F

Since the delay on the second block 16 exceeds the total delay delay on the first and second registers 17 and 18 and element 19, the pulse generated by the second generator 13 and delayed by the second block 16 enters the first, second and third elements AND 20 - 22 after the element 19 generates a signal corresponding to the ratio of the codes. If the frequency on the first input bus 28 is higher than the frequency on the third input bus 30 (Fig. 2a, 6) s, then the phase shift between the input pulses increases, the value of the code in each subsequent period becomes smaller, and element 19 generates a signal at output A f In (Fig. 2;). In this case, the impulse with

35

Q

50

s

five

the output of the second block 16 of the delay device through the first element AND 20 and the fourth element OR 26 sets the third trigger 9 to one state and a signal is transmitted to the second output 32 (Fig. 2n). If the frequency on the first input bus 28 (Fig. 2a) is lower than the frequency on the third input bus 30 (Fig. 26), element 19 forms a signal at output AB (Fig. 2k) and a pulse delayed by the second block 16 through the second element Both 21 and the first1 element OR 23 sets the first trigger 6 to one state and the third trigger 9 zeroes through the OR 24 element. At the first exit 31 a signal appears (Fig. 2m) and at the second exit 32 the signal disappears (Fig. 2n ). If the frequencies on the first and third input buses 28 and 30 are equal, the element 19 generates a signal at output A - B, and the pulse from the output of the second block 16 sets the fifth trigger 10 into one state and through the second and fifth elements I 2 and 27 swings the first and fourth triggers 6 and 9.

Thus, with a significant mismatch of the input frequencies, they are compared by the frequency difference separation unit 11, with the first and second triggers 6 and 7 or the fourth and third triggers 9 and 8 being set to the one state. or the third 8 flip-flops block the passage of a pulse from the output of the second block 16, excluding the operation of element 19 (FIG. 2d, n). With a small difference in frequency, they are compared by element 19.

The rest of the device's tapes work as described above. The combination of signals at the outputs of the three channels allows determining the ratio of input frequencies. From the description of the operation of the device, it follows that the first output buses 31, 3 and 37 of the first, second and third channels 1 - 3 signal the signal if the frequency at the first input of the channel is lower than the frequency at the second input of the channel, at the second output tires 32, 35 and 38 the first, second and third channels 1 - 3 signal is generated, if the frequency at the first channel input is higher than the frequency at the second channel input, the third output buses 33, 36 and 39 of the first, second and third channels 1 - 3 signal is generated when the frequencies at the inputs are equal channel.

The redundancy of the outputs allows the discrimination of input frequencies with increased reliability, i.e. failure of any element of the device does not affect the final result.

Since the output signals are generated according to the results of processing the current and previous periods, the signals at the outputs of the discriminator change immediately after the change in the difference of the input frequencies. This increases the accuracy of the frequency selection in terms of changing input frequencies.

Claims (1)

Claim 20 Digital pulse frequency discriminator containing identical first, second and third signal processing channels, each of which contains a first pulse counter, first to fourth triggers, the output of the first trigger connected to the first output of this signal processing channel, the first inputs of the first, second and The third signal processing channels are connected to the first, second and third input buses, respectively; the first outputs of the first, second and third signal processing channels are connected to the first group of output buses these channels, the first input of the first signal processing channel is connected to the second input of the second signal processing channel, the first input of the second signal processing channel to the second input of the third signal processing channel, the first input of the third signal processing channel to the second input of the first signal processing channel, that, in order to increase the selection accuracy, frequency, a differential frequency separation block, the first, second and third pulse shapers, the second pulse counter, were introduced into each of the signal processing channels, the first trigger, the first and second delay blocks, the first and second registers, the comparison element, the first, second and third AND elements, from the first to the fifth OR elements, with the first input of each signal processing channel connected to the first input 25 20 the house of the differential frequency allocation unit, with the counting input of the first pulse counter and the input of the first pulse generator, the second input of each signal processing channel is connected to the second input of the differential frequency selection block, to the counting input of the pulse counter, and to the inputs of the second and third pulse formers, first output the difference frequency selection block is connected to the S input of the second trigger and the first input of the first OR element, the output of which is connected to the S input of the first trigger and to the first inputs of the second and third of the OR elements, the second output of the differential frequency selection block is connected to the S input of the third flip-flop and the first input of the fourth OR element, whose output is connected to the S-input of the fourth flip-flop, to the second input of the third OR element, and to the first input of the fifth OR element, the second inputs of the fourth and first elements OR are connected respectively to the outputs of the first and second elements AND, the first inputs of which are connected to the outputs of the second and third triggers, respectively, to the R inputs of the first and second counters, respectively, and also to the first; th and the second inputs of the third element And, respectively, the output of which is connected to the S-input of the fifth trigger and the second inputs of the second and fifth elements OR, and the output of the first pulse former is connected to the input of the first delay unit, the outputs of which are connected in bit with D- inputs of the first register, the output of the second pulse driver is connected to the input of the second delay unit and to the C inputs of the first register, the outputs of which are bitwise connected to the D inputs of the second register and to the first group of inputs of the comparison element, the second group the inputs of which are connected in parallel to the outputs of the second register, while output A: B of the comparison element is connected to the second input of the first element I, output AB of the second input of the first element I, and output A B of the third input of the third element I the pulse former is connected to the C-inputs of the second register, the output of the second delay unit is connected to the third inputs of the first and second 30 35 40 45 50 55 eleven And with the fourth input of the third element And, the outputs of the first and second pulse counters are connected to the C inputs of the second and third triggers, respectively, and the outputs of the fourth and fifth trigger I 15823М12 The ditch is the second and third outputs of the signal conditioning channels and is connected respectively to the second and third output buses of this signal processing channel. FIG. 2