SU1635270A1 - Device for discrete-and-phase locking - Google Patents

Abstract

The invention relates to discrete information transfer systems. The purpose of the invention is to reduce the time of occurrence of synchronism for large phase mismatches of the input and reference signals. Device dis

Description

Phage L

Phase synchronization contains the shaper 1 pulses of the input sequence, phase discriminators 2, 7 and 8, blocks 3 and 9 of reverse averaging, addition block 4 - exclusion of pulses, generator 5 of the reference pulse sequence, pulse counter 6, the element OR 10 and demultiplexer 11. V the phase discriminator 2 determines the sign of the phase mismatch between the impulses of the input sequence and the pulses of the phased sequence coming from the first output of the demultiplexer 11. The corresponding unit 4 moves through the unit 3 receives the control pulses yupsche. As a result, in the reference sequence of the pulses of the generator 5, the period changes to Do with each exclusion or addition of pulses. When the phase mismatch is larger than the preselected value ± DT0, in parallel with the above described phase discriminators 7 and 8, pulses are generated to block 9, from the output of which, through the OR 10 element, an input is sent to the installation O of counter 6, which causes the formation on the first output of the demultiplexer 11 output sequence, in phase with the input. 2 Il.

The invention relates to systems of discrete information transmission and can be used in time synchronization systems.

The purpose of the invention is to reduce the time taken to synchronize with large phase mismatches of the input and reference signals.

FIG. 1 shows a block diagram of a discrete phase synchro-device; FIG. 2 - time diagrams of his work.

The discrete phase synchronization device contains the shaper 1 of the input sequence pulses, the first phase discriminator 2, the first block 3 of reverse averaging, the block 4 for adding and excluding pulses, the generator 5 of the reference pulse train, the counter of 6 pulses, the second phase discriminator 8, the second block 9 reverse averaging, the element OR 10, the demultiplexer 11.

The capacity N of the first reversal averaging unit 3 is selected by several units less than the capacity N of the second reversal averaging unit 9, N, M being N1.

At the first output of the demultiplexer 11, pulses appear when there is a code combination on the control input

zero from the counter 6 pulses whose capacity is equal to the number n, where n is equal to the frequency ratio of the generator 5 of the reference pulse sequence and the sequence at the output of the demul

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the type of the terminal 11. The signals from the first output of the demultiplexer 11 are shown in figv. The signals at the second output of the l - multiplexer 11 (FIG. 2d). correspond to the code combination p / 2, i.e. the phase shift between these sequences is half the period. The signals from the third and fourth outputs are formed, depending on the code combinations at the control input of the demultiplexer 11, so that the corresponding sequences (fig.2d and 2e) determine the interval of phase deviation values greater than the preselected values.

The device works as follows.

In the first phase discriminator 2 (Fig.2l and 2m), the sign of the phase mismatch between the pulses of the input sequence (fig.2b) and the phased sequence pulses from the first output of the demultiplexer 11 (figv) is determined. To the corresponding inputs of the add-exclude-pulses unit 4, through the first reversible averaging unit 3 (fig. 2n and 2 °), add-exclude control pulses are received. As a result, in the reference sequence of the pulses of the generator 5 (FIG. 2a), the period changes by Db with each exception or addition of pulses. From the output of the add-exclude-4 block, the pulses (Fig. 2g) of the reference sequence are fed to the counting input of counter 6 and to the switched input of the demultiplexer 11, at the first output of which an output sequence of pulses is formed (Fig. 2c).

When the phase mismatch is larger than the preselected value of j D.T0 in parallel with the operation of the circuit described above, the following occurs: in the second 7 (Fig.2z) or the third 8 (Fig.2i) phase discriminator (depending on the sign of the phase mismatch) it is found that the magnitude of the error is greater than the preselected value of & T0, and the corresponding pulses are generated, which are fed to the second block 9 by reversing the averaging, from the output of which, through the OR 10 element, a pulse arrives at the installation input in O of the counter 6 pulses falling in phase with pulses of the input sequence. In this case, the pulse counter 6 is set to O and at the first output of the demux of the multiplexer 11 (Fig. 2b), which is the output of the device, an output sequence of pulses is formed, in-phase with the input sequence from the exact signal output, i.e. . a jump-like adjustment of the phase of the output sequence occurs.

When the phase mismatch & 1, D G0 pulses from the outputs of the first and second phase discriminators 2 and 7 (Fig. 2l, 2m and 2) are received respectively in the first 3 and second 9 blocks of reversible averaging. The first is filled with the first reversing averaging unit 3 having a capacitance NJ, and the phase mismatch is reduced by L, i.e. becomes equal to & Tg & T, - & Ј (Fig. 2B). Provided that & T TQ and that the capacity N of the second reversible averaging unit 9 is greater than the capacity N of the first block 3, the second block 9 is filled in through (N) pulses after filling the first reversing averaging device 3 and FIG. ) to the input of the installation of the pulse counter passes a pulse coinciding in phase with the input sequence. A pulse counter 6 is set to O, which causes the appearance on the transducer.

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the output of the demultiplexer 11 pulse, coinciding in phase with the input sequence (Fig.26 and 2B), i.e. There is a quick adjustment.

Claims (1)

Invention Formula A discrete phase synchronization device containing a series-connected pulse shaper of the input sequence, whose input is an informa- tional input of the device, the first phase discriminator, the first reversing averaging unit, the addition-subtraction unit of imputas, and a pulse counter, at which the generator output is signals are connected to the corresponding input of the addition unit — the pulse calculation, which is, so that, in order to reduce the time taken to synchronize for large ph govyh mismatch x input and reference signals introduced fazosye second and third discriminators, reverse usrrlnonin second block, chpement OR demupt IPPS hBD par to mfavpnyu- conductive inputs of which are connected outputs impuchson counter, the counting input of which a switched input soedinrts demultiplexed. the first output of which is SORDINRN of the shaper of the positive mismatch interval of the first function of the discriminator and is the current of the device; the inputs of the OR element, the output of which is connected to the input of the pulse counter installed in O, the second output of the demultiplexer being connected to the hopper to form a negative speaking first 0 of the phase discriminator and with the inputs of the formation of the intervals of the positive mismatch of the second and third phase discriminators, to the inputs of the formation of the intervals of the negative mismatch of which are connected to the third and fourth outputs of the demultiplexer. 0 0 five