SU1198560A1 - Device for displaying information on screen of cathode- ray tube - Google Patents

Description

The invention relates to automation and computer engineering and can be used in devices for displaying information output from an electronic computing ₅ machine or / and any other sensors of digital information on a CRT screen.

The purpose of the invention is to improve the device performance by allowing the device to make a short turn to the device while at the same time eliminating distortions of the reproduced image and time to regenerate the reproduced information. 15

1 shows a block diagram of the device ·, figure 2 is a timing diagram of the operation of the device.

The device contains 1 pulse generator, 2 clock counter, pulse distribution encoder 3, reference encoder 4, first element 5, regeneration address counter 6, second element 7, playback address counter 8, data register 9, address register 10, memory block 11 , CRT 12, read trigger 13, write trigger 14, element OR 15, address switch 16, playback playback buffer registers 17 18 output data, switch 19 pulses, sequence of elements in a row, loop control trigger 20, address encoder 21, counter 22 item numbers per row ke, trigger 23 synchronization, the divider 24 frequency. _χ

2

At input 25, control signals are supplied from an external source, for example a computer (not shown), at input

26 - input data code, by input

27 - the input code of the data address; at the output 28 - the output signal of the sign of the write-read cycle in the computer - receiver of information (not shown), at the output 29 - output data code.

A device for displaying information on the screen of a CRT works as follows.

The generator 1, the counter 2 and the encoder 3, which are connected in series, form a cyclic sequence of control impulse signals (figure 2 <0) according to duration and period (repetition frequency).

Lowercase and frame sync pulses from the output of the encoder 3 are fed to the inputs 30 and 31 of the CRT 12 and through the horizontal and vertical sweep generators, the lowercase and personnel deflection coils of the CRT (not shown), turn the beam from left to right and from top to bottom in accordance with the television standard. The modulation pulses from the output of the switch 19 are fed to the input 32 of the modulation of the CRT 12 and through the modulation amplifier of the video pulses (not shown), illuminates the set points of the raster deployed on the screen of the CRT 12, forming a reproducible image.

All information about the reproduced image is stored in block 11

3

1198560

four

memory (randomly selected) the number of words in block 11 is equal to the number of elements of the decomposition of the image on the CRT 12 screen (the product of the number of elements of the decomposition in a raster line by the number of lines in the raster). Between the address of each word in block 11 and the address of the decomposition element There is a one-to-one correspondence on the screen of the CRT 12. The word length of each word in block 11 is determined by the number of reproduced brightness gradations (semitones) on the screen of the CRT 12 and in the simplest case for a black and white image is one bit (one bit). information on the CRT screen 12 should be at a frequency above the critical frequency of the picture elements and flicker component for progressive television standard of 50 Hz, i.e. a frequency of each word must be read from the storage unit 11.

For a line-by-TV standard, with 256 lines per frame and 512 decomposition elements per line (this number with some margin equals the resolution of television CRTs), block 11 for a black and white image is 256 · 512 = 2 ^{3–2 , =} 2 ¹⁷ bits

A block of memory of this size is usually built on a dynamic type of chip.

However, for a block of memory of a dynamic type, a constant information with a certain regeneration cycle is necessary to record the recorded information in order to avoid spontaneous erasure of the recorded information.

Information change in block 11 when recording from an external source of information (for example, a computer) or reading information from block 11 to an external source of information (for example,

A computer) for analyzing and processing this information requires corresponding write-read time cycles for block 11, and taking into account the large volume of block 11 and, accordingly, large amounts of written and read information, the total time of these write-read cycles can be quite large.

Thus, there are three mutually independent reasons for referring to block 11: reading when resuming information on the screen of a CRT 12, regeneration of information, writing-reading information from external sources of information.

Interruption of reading from block 11 when resuming information on the screen of a CRT 12 for regeneration or writing-reading from external sources of information leads to flickering,

10 flicker of the reproduced image, the appearance of stripes, lines of different inclination and points on the reproduced image. All this causes increased fatigue and, as a consequence, an increase in the number of errors made by the operator in the mode of interactive interaction with computers.

The regeneration of the information of block 11 and the recording-reading of information in block 20 11, carried out during the return stroke of the horizontal and vertical scanning, exclude the indicated interferences on. reproduced image, at the same time significantly reducing the speed of 25 write-read from external sources of information, which is undesirable given the large amounts of recorded and readable information. Since the cycles of regeneration of information in the memory block have priority over the write-read cycles, the write-read speed during reverse moves along the line and frame is further reduced due to regeneration by about two times.

The device implements a priority-free call to block 11, in which the distortion of the reproduced image is completely eliminated

at maximum write speed40

reading from external sources of information and guaranteed regeneration of memory block 11.

The address of the word in block 11 is set by the switch 16, the address inputs of which, in turn, are connected to counters 6 and 8 and register 10.

Counting plus units at the input 33 of the counter 6 are generated by the element And 5, at the input 34 of the counter 8 by the element And 7. The address code in the register.

10 enters at input 27 when the trigger 14 is set to one.

55 Data in block 11 at input 35

recorded at input 26 through re. gistr 9 when set to one

• trigger 14.

5 and

The control signals for row and column selection, write-read, regeneration, chip selection are received at the ’input 36 of block 11 from the output of the encoder 4.

The output of block 11 is read into registers 17 or 18.

In turn, the information from the output of the register 17 - the code of the group of reproduced elements is fed to the input 37 of the switch 19, the ac output of the register 18 - to the output 29 (output data for recording to external receivers of digital information).

The time of one (even or odd) partial cycle of reference (writing or reading) to block 11 is equal to its own minimum time {cycle of circulation of block 11.

The time of one complete cycle of addressing T to block G1, which is necessary for the realization of the non-priority address to block 11, consists of two partial cycles, i.e. T =

= 2 {.

During the even partial cycle, information is read to resume the image on the CRT 12 screen; during the odd partial cycle, recording-reading from external sources of information or ’regeneration takes place. Thus, reading to restore the image and writing-reading from external sources of information or regeneration occurs 35 in disjoint lengths of time, i.e. there are no conflict situations between the above procedures in the process of referring to block 11,

Write-read information from external θ ⁴ are information sources takes place in the same time period, however when there is a sign of regeneration zapisichteniya blocked (traditionally regeneration nai- ⁴⁵ has the highest priority relative to all other treatment procedures to block 11, but it completely optional). As indicated, in order to write-read information from the external ⁵⁰ information sources, three commands should be received in block 11, of which one command is the cycle for accessing block 11, i.e. of the three consecutive even partial 55 cycles of reference to block 11 in the worst case, two cycles are allotted for regeneration.

98560 6

At the input 38 of the counter 22 from the output of the generator 1 receives pulses with a period of £. Counter 22 counts

modulo AND, i.e. after each and 5 impulses is reset to zero. At the beginning of the forward stroke on the line and at the beginning of the forward stroke on the frame, the counter 22 is set to zero by forward pulses on the row and frame through 10 input 39 and from the output of the encoder 3.

The code from the output of the counter 22 to the address input 40 switches the switch 19, which the parallel code from the output of the register 17 to the input 37 converts into a serial pulse modulation code to the input 32 of the CRT 12.

Writing-reading information from external sources of information is carried out in odd partial cycle 20 also in bit words. '

The number of even-odd cycle determines the trigger 20, the input 41 of which the output of the divider 24 receives the counting pulses with a frequency

²⁵ equal to the frequency of the generator 1 divided by And / 2. Setting zero of trigger 20 to input 42 is carried out at the beginning of each forward stroke of ¹ line with a forward stroke pulse of 30 lines from the output of encoder 3.

The encoder 21, the input 43 of which is connected to the output of the trigger 20, generates for the switch 16 the address code by which the switch 16 connects to the input 44 of the address of block 11 or the address code from the output of the counter 8 in the even partial cycle, or the address code of the counter 6 or register U in an odd partial loop. The input 45 of the encoder 21 is connected to the output of the trigger 23, which introduces into synchronization the asynchronous write-read signals from external sources of information, which from input 25 arrive at the installation input to unit 46 of the trigger 13, or 47 trigger 14, are remembered by the specified trigger: and by inputs 48 and 49 through the element OR 15 are received at the information input 50 of the trigger 23. On the synchronous input 51 of the trigger 23, a signal is output from the output of the trigger 20. Therefore, the installation of the trigger 23 in the unit is tied to the device’s common clock pulses generated by the generator rum

1. During the odd partial cycle of reference to block 11, immediately after the installation of the trigger 23 in the unit7 1198560

eight

tsu, there is a recording-reading of information from external sources of information in block 11. A single signal from the output of the trigger 23 is fed to the input 52 of the element 5, blocking 5

counting plus units at its output, to input 53 of register 18, allowing writing information from the output of block 11 to register 18 when reading to external sources of information, to input 10 45 of the encoder 21, which through switch 16 connects to the address bus block 11, register 10, at exit 28, a sign of readiness for the next recording — reading to external sources of information.

At the end of the odd cycle of access to block 11, the falling edge of trigger 20 is reset to zero at input 51, trigger 23, which in turn at inputs 54 and 55 resets trigger 13 or 14 to zero.

Write to the register 9 input code

when installing the trigger 20 in the unit.

Writing into the information register 18, from block 11 at input 56, is performed when trigger 13 is set to one during an odd partial circulation cycle. During the odd cycle of circulation, the passage of the counting units plus the input 33 of the counter 6 through the AND 5 element is also permitted when the trigger 23 is set to the zero state.

During the even partial cycle, writing is made to the register 17 of block 11, passing the counting units plus the input 34 of the counter 8 through the And 7 element during the forward run through the row and frame.

The encoder 4 generates control signals at its output for block 11, depending on the states of the flip-flops 13, 14, 20 and 23 (inputs 57-60, respectively) and clocks

1198560

α 72 3873

Μ-Μν Π_Π Π_Π

53,61,64,70.71,1 / 3.51 g

L? Γ ~: I_3-Ι__Ι-1__ | -1_

28,32,5Ϋ _} 55, 53, Yu | -'- 1__

Odam from breathing. saenahgod encoder 3

L _: _

& and <?. Ζ

Claims (1)

DEVICE FOR DISPLAYING INFORMATION ON SCREEN ELECTRON-BEAM TUBE (CRT), containing sequentially connected first element AND and the address of the regeneration address, memory block, data register, element OR, second element And, the counter address play, the read trigger, address register, pulse generator , recording trigger, clock counter, pulse distribution encoder, access encoder, pulse generator output connected to clock pulse input, the output of which is connected to the input of pulse distribution encoder, the output of which connected to the inputs of the CRT sweep, with the first input of the access encoder, with the input of the second element And with the first and second inputs of the playback counter, the output of the second element And connected with the third input of the playback address counter, the output of the write trigger — with the inputs of the data registers and the address and the second input of the access encoder, the output of which is connected to the first input of the memory block, the second input of which is connected to the output of the data register, the output of the reading trigger ’is connected to the first input of the element OR and the third input of the access encoder, the second input of the OR element is connected to the output of the recording trigger, characterized in that, in order to increase the device performance by allowing non-sequential access to the device while simultaneously excluding distortions of the reproduced image and time for regeneration of the reproduced information, it contains an address switch, two buffer registers, a cycle control trigger, an encoder ί,. addresses, the number of elements in the row counter, the pulse switch of the sequence of elements in the line, the synchronization trigger and the frequency divider, the output of the address switch is connected to the third input of the memory block whose output is connected to the first inputs of the first and second buffer registers, the second, third and fourth inputs the second buffer register is connected respectively to the outputs of the cycle control trigger, the synchronization trigger and the read trigger; the second input of the first buffer register is connected to the output of the control trigger cycle ohm, and the output - with the first input of the switch of pulses of a sequence of elements in the row, the second input of which is connected to the output of the counter of the number of elements in the row, and the output of the backlight of the CRT, the first and second inputs of the counter of the number of elements in the row, are connected respectively to IC 1198560 1198560 with the outputs of the pulse distribution encoder and the pulse generator, the input of the frequency divider is connected to the output of the pulse generator, and the output is connected to the first input of the cycle control trigger, the first input of the first And element and the third input of the second And element, the output of the synchronization trigger is connected to the first read trigger input , the first input of the address encoder, the first input of the record trigger, the fourth input of the encoder calls the second input of the first element And, ^ the second the input of the cycle control trigger is connected to the output of the pulse distribution encoder, and the output is connected to the third input of the first element And, the fourth input of the second element And, the second input of the address encoder, the second input of the synchronization trigger and the fifth input of the access encoder, the second input of the synchronization trigger connected to the output of the OR element , the inputs of the address switch are connected respectively to the outputs of the playout address counter, the address register and the address coder. one