SU1510009A1 - Device for shaping addresses of buffer storage - Google Patents

Abstract

The invention relates to computing and can be used in blocks of buffer memory. The purpose of the invention is to expand the field of application of the device by generating current addresses for specified areas of the buffer memory. The device contains memory block 1, first arithmetic logic unit 2, register 3, element 4, counters 5, 6, reset signal generator 7, adder 8, code converter 9, second arithmetic logic unit 22. These devices are intended for generating addresses of the buffer memory in the devices for receiving and transmitting data over a compacted communication line with a temporary seal of the channels. The time-multiplexed path is two lines: a line of transmitted data and a line of received data, through which information is transmitted and received on several channels respectively. In each channel slot, one data word is transmitted and received. 2 ill., 1 tab.

Description

cl

with

The invention relates to computing and can be used in blocks of buffer memory for data receiving and receiving devices over a compressed communication line, as well as in automatic connection devices in automatic switching systems.

The purpose of the invention is to expand the scope by forming current addresses for specified areas of the buffer memory.

Figure 1 shows the block diagram of the device; figure 2 - timing diagram of the device.

The device (Fig. 1) contains a memory block 1, a first arithmetic logic unit 2, a register 3, an AND 4 first .5 and a second 6 counters, a shaper of 7 reset signals, an adder 8, a converter of 9 codes,

the first 10 and second 11 synchronization inputs, input 12 load, record 13 input, first 14 and second 15 status inputs, first 16 and second 17 device outputs, output 18 of counter 5, memory block output 19, output 20 of counter 6, output 21 shaper 7, the second arithmetic logic unit 22.

The device is intended to form addresses for the buffer memory of data receiving and transmitting devices through a line, and communication with temporary channel multiplexing, in particular, via PCM paths in digital PBXs. The PCM track is a line of transmitted data and a line of received data on which information is transmitted and received on 32 channels respectively. In each channel slot, one data word is transmitted (via the transmit path) and received (by the receive path).

On each channel, one data word can be received (via the receive path) and transmitted (via the transmit path).

In each channel, a message may be received (via the receive path) and transmitted (via the transmit path). The device provides up. sending or receiving a message word packet for each channel, either without confirmation or with a confirmation, with a message for each word message1-1, the latter mode can be used in automatic devices

five

0

five

0

five

0

five

0

five

to establish connections to automatically send commands to control switching through the digital switching field with confirmation on each command.

Reception and transmission of information can be carried out in parallel across all channels. To be able to simultaneously receive messages for each channel and write them to the buffer memory and. Transmitting messages from the buffer memory, it is necessary to store and output the current addresses of the buffer memory for each of the 32 channels (transmitting and receiving), while transmitting or receiving words messages without confirmation it is necessary to ensure that the corresponding channels increase the address by one in each cycle. When transmitting with acknowledgment, it is necessary to increase the address of the corresponding channel only if acknowledgment is detected on the receiving channel. These functions are performed by the proposed device.

Since the messages are not received and transmitted simultaneously, the current addresses for the buffer memory areas corresponding to different channel slots will be different. The device has the first counter 5, which forms the current samples, and the initial samples for each channel interval are recorded and stored in memory block 1. The first arithmetic logic unit 2 ensures the formation of the current address by some operation on the state of the first counter 5 and the contents of the MbiM of the memory 1. The slot number (address of the buffer memory area) is generated by the second counter 5.

Thus, the device performs a function of 2K counters, where K is the number of time slots, since the addresses are formed for both the reception and the transmission. By using: relative readings, periodic self-initialization of current addresses is provided, which increases the reliability of the device.

The second arithmetic logic unit 22 is designed to calculate the code recorded in memory block 1 in the transmission mode with confirmation for each transmitted word of the message.

The operation code for arithmetic logic units generates a code converter 9, depending on the state of the first synchronization input 10 and the device status inputs 14 and 15.

The second device sync input (input 11) is a frame synchronization input and is intended to synchronize the zero time slot. The differential 0-1 of the frame alignment signal shaper 7 generates a reset signal (figure 2) of the slot counter (counter 6) and sets the zero channel interval.

The first synchronization input of the device (input 10) is the input of channel synchronization and is intended to synchronize the time slots. By the 1-0 difference of the channel synchronization signal, the state of the slot interval counter (counter 6) changes by one. A 1-0 signal is also used to divide the channel interval by the transmit and receive cycle (Fig. 2). A 1-0 signal is also applied to the address input of memory unit 1 and divides the memory into two regions. In the state O of the input 10, the device operates for the receiving path, and in the state 1, for the transmitting path.

At the device download input (input 12), a code is provided from the output of block 2 to register 3 to receive the current address for the current channel at device output 16 (first for receiving, then for transmitting).

The device's write input (input 13) is intended for gating the write to memory 1, depending on the state of the second output of the code converter 9.

Counter 6 is determined from a number of channel slots with a time stamp. For 32 channels, the counter size is 5,

The length of the counter 5 is determined from the maximum message length on one of the channels. With a maximum length of one message (64 bytes), the counter 5, like the memory block 1, is 6.

Counter 5 is designed to form the current reference for. you5

number of current addresses. The memory unit 1 is designed to record and store relative samples for each transmitter and each receive channel. With the number of channels 32, the capacity of the memory block 1 is 64 words. Counter 6 generates the channel interval number (the address of the buffer memory area). The adder 8 is designed to match the 1 and the delay of the input and output information received and transmitted from the buffer memory.

In reception cycles, the adder 8 decreases the state of the counter 6 by 1, and in the transmission cycles it increases by 1.

Figure 2 shows the timing diagram of the device. Each

The Q anal interval is divided into four cycles of accessing memory block 1 — read, write, read, write (the first two calls to receive, the second to send).

5 The table shows an example of the operation of arithmetic logic units with different states of inputs 14 and 15, to which the bits of received and transmitted data are assigned, determined by the information code.

The generation of current addresses is accomplished by a block, which in reception cycles performs operation C-B-1, where C is the state of output 18 of counter 5; B - output state 19 of block 1 of one 5 m. In the transmission cycles, the block performs the operation C-B-1 in all cases, except the case of receiving a positive acknowledgment on a certain channel in the mode of sending commands. In the latter case, block 2 performs a C-B operation, which allows the current address to be incremented by one to form the address of the next command. The change in the function of block 2 is performed by the code converter 9, which in reception cycles converts the state of the device input 14 into the code of the corresponding operation.

Block 22 generates a code that is recorded in memory block 1 for each transmitter and each receive channel. In reception cycles, block 22 performs the function D C, except for the case of receiving a code. Positive confirmation when block 22 is transferred by the converter 9 codes to the execution of operation D C – E, where E is the output state 16 of the device; D - so0

five

0

the output of the block 22. In the transmission cycles, block 22 performs the function D C - E when transmitting a command or wait, or if a positive acknowledgment is detected in the receiving channel. In the remaining cases, block 22 performs operation D C. In the initial state in cycles write to memory 1, the state of the counter 5 is constantly recorded. The write pulse passes through the element ANDA to the input of memory 1, In the read cycles of memory 1, the value written to memory 1 in the same channel interval is read the previous cycle, in this case, block 2 performs the operation A C - - B - 1, as a result of which the register 3 is loaded and at the output 16 of the device for Bc fex channels a code zero is generated (B C - 1) - initial current addresses for each channel (receiving and transmitting), Thus, at the output 16 of the device, current addresses are formed for each channel, the code of which is removed from the output 17 of the device.

When a message arrives (code Message at device 14), the recording in block 1 of the memory is prohibited (in the corresponding channel interval). Thus, for the channel interval on which the message arrives, in memory block 1 at the address equal to the channel interval number, the value С preceding the appearance of the code remains. Message at input 14. Thus, in the corresponding channel interval in the receive cycles when receiving a message, the address is incremented by one for each word of the message.

When a message is sent (the message code at device input 15), the same actions are performed as when a message was received, except that everything happens in transmission cycles and the state of input 15 is analyzed,

When transmitting information (commands) with confirmation, it is necessary to ensure the delay of transmission of the next command until a positive confirmation code is received on the receiving channel, for example, from the side of the digital switching field, informing you about the execution of the call setup command. To this end, after issuing the command to

0

Q 5

-. . S

five

0 j

the same cell of the buffer memory is recorded with the Waiting code.

When sending a command, block 22. is set using converter 9 of codes to execute the function D C - E (E is the output 16 of the device, D is the output of the block 22.), so that the block 1 of the memory records the code that when the block 2 executes the function A C - B - 1 in the next cycle in this channel interval will repeat at the output 16 of the device the address of the previous cycle, as a result of which the Waiting code is received from the buffer memory. When the Waiting and Command codes are detected, the block 22 is set to execute the D C-E function. In the next cycles in this channel interval, the same address will be provided in the transmission cycles until a positive acknowledgment code is received on the receiving channel.

In this case, block 2 is set to perform function A C – B, which causes an increase in the address code at output 16 by one, i.e. output from the buffer memory of the next command. When this block 22 is set to perform the function D C-E

The Confirmation, Command and Waiting codes are fed through the inputs 14 and 15 of the device to the converter of 9 codes. The device input 10 selects the dp conversion by block 9 or the code from input 14 (for reception), or from input 15 (during transmission). Block 9 allows the operations of the arithmetic logic units 2 and 22 to be changed.

A change in the operation of block 2 with A – C – B – 1 to A – A – C makes it possible, when receiving a positive acknowledgment, to speed up the output | of the following command by one cycle.

Invention Formula

A device for generating buffer memory addresses containing a memory block, a register, an AND element, a first arithmetic logic unit, first and second counters, an adder, a shaper of reset signals, the register output being the first address output of the device, the register loading input the device load input, the first address input of the memory block is the first sync input of the device, input syn91510

The timing of the first counter is connected to the input of the reset signal generator and is the second synchronization input of the device, the output of the reset signal generator is connected to the installation input of the second counter, whose outputs are connected to the inputs of the first group of the adder, the inputs of the second group of which are connected to the first synchronization input of the device and the synchronization input of the second counter, the outputs of the adder are connected to the address inputs of the group of the memory block and are the second address terminal of the device, the first input of the AND element is the write-read input of the device, the element ID code is connected to the write-read input of the memory block with the information inputs of the first group of the first arithmetic logic unit, the information inputs of the second group of which are connected to the memory block outputs, the outputs of the first arithmetic logic unit are connected with the inputs of the register

five

0

five

ten

In order to expand the field of application of the device by forming current addresses for specified areas of the buffer memory, a second arithmetic-logic unit and a code converter are inserted in it, the first synchronization input of the device is connected to the control input of the code converter, the inputs the first and second state groups of which are the corresponding inputs of the device, the outputs of the first group of code converter are connected to the control inputs of the first and second arithmetic logic units, t The code converter code is connected to the second input of the element I, the outputs of the first counter are connected to the information inputs of the first group of the second arithmetic logic unit, the outputs of which are connected to the information inputs of the memory block, the outputs of the register are connected to the information inputs of the second group of the second arithmetic logic b: 1ka.

Note, X is an arbitrary state.

/ njnjTjajnjnjTTLnj Lj-Lnj-LTLTb

I Channel 0 I

FIG. I

Compiled by Y. Sychev Editor A, Motyl Tehred A. Kravchuk

Order 5822/52

Circulation 558

BHlffiltti of the State Committee on Inventions and Discoveries under the State Committee on Science and Technology of the USSR 113035 Moscow, K-35, 4/5 Raushsk nab.

Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101

gp

„M

Channel 1

Proofreader S. Shekmar

Subscription

Claims (1)

Claim A device for generating buffer memory addresses, comprising a memory unit, a register, an AND element, a first arithmetic logic unit, a first and second counters, an adder, a reset signal conditioner, and the register path is the first address output of the device, the register load input is the device boot input, the first address input of the memory block is the first synchronization input of the device, the synchronization input of the first counter is connected to the input of the reset signal generator and is the second synchronization input of the device, the output of the reset signal generator is connected with the installation input of the second counter, the outputs of which are connected to the inputs of the first group of the adder, the inputs of the second group of which are connected to the first input device synchronization and synchronization input of the second counter, the outputs of the adder are connected to the address inputs of the group of the memory block and are the second address output of the device, the first input of the element And is the write-read input of the device, the output of the element And is connected to the write-read input of the memory block, the outputs of the first counter connected to the information inputs of the first group of the first arithmetic-logical unit, the information inputs of the second group of which are connected to the outputs of the memory unit, the outputs of the first arithmetic-logical b eye connected to the inputs of the register of Whitlock u1 '*? * characterized in that, in order to expand the scope of the device by generating current addresses for specified areas of the buffer memory, a second arithmetic-logical unit and a code converter are introduced into it, the first synchronization input of the device being connected to the control input of the code converter, the inputs of the first and the second state groups of which are the corresponding inputs of the device, the outputs of the first group of the code converter are connected to the control inputs of the first and second arithmetic-logic blocks, the second the output of the code converter is connected to the second input of the And element, the outputs of the first counter are connected to the information inputs of the first group of the second arithmetic-logical unit, the outputs of which are connected to the information inputs of the memory block, the outputs of the register are connected to the information inputs of the second group of the second arithmetic-logical bDock. Reception Broadcast the confirmation Operation Block 1 of memory Co- joint Entrance 14 Entrance 15 ALU 2  ALU 22 Command Expectation I will confirm Message Com- Yes Expectation 0 0 0 0 X X X X A = C-B-1 D = C Record 1 0 0 0 X X X X A = C-B-1 - -  0. 0 1 0 X X X X A = C-B-1 D = C Record 0 . 1 0 0 X X X X A = C-B-1 D = C Record X X X 1 X X X X A = C-B D = CE Record X X X X 0 0 0 0 A = C-B-1 D = C Record X X X X 1 0 0 about A = C-B-1 - - X X X X 0 0 1 0 A = .C-B-1 D = CE Record X X X X 0 1 0 - 0 A = C-B-1 D = CE Record X X X X 0 0 0 1 A = C-B-1 D = C Record: Note. X is an arbitrary state. 30 31 O 7 I Channel 0 \ Channel 1 ΓΊ J ~ l P. PL FIG. Z