SU1310829A1 - Interface for linking information source with communication channel - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in discrete information transmission systems. The aim of the invention is to expand the functionality of the device by transmitting to the source of information a receipt for freeing the memory in code form. The device contains the element OR NOT 1, the counter 2 of the memory address, the switching unit 3, the trigger 4 transmissions, the element OR 5, the block 6 memory, the analyzer 7 combi-. nations of the boundary code, control counter 8, element 9, bus driver 10, overflow trigger 11, line trapping unit 12, NOT element 13, first 14 and second 15 address generation blocks, comparison block 16, application 17 trigger, trigger 18 is busy tosti. By introducing triggers and address generation blocks, the device can identify the message intended for it and inform the source of information about readiness to send the next message by writing a receipt for clearing the data on the information highway in the form of the address code of this device. 1 hp f-ly, 6 ill. (L co ge co

Description

The invention relates to computing technology and can be used in discrete information transceiver systems.

The purpose of the invention is to expand the functionality of the device by transmitting to the source of information a receipt for freeing the memory in code form.

FIG. 1 shows a functional diagram of the device; on fi-g. 2 - diagram of the analyzer combination of the boundary code; FIG. 3 is a diagram of an address generation block; FIG. 4 is a timing diagram of the operation of the boundary code combination analyzer; Fig.5 is a block diagram of the switching unit and timing diagrams of clock signals; 6, an example of the use of the device.

 The device contains the element OR NOT 1, the counter 2 of the memory address, the switching unit 3, the trigger 4 transmission, the element OR 5, the block 6 memory, the analyzer 7 of the combination of the boundary code control 8, the element 9, the bus driver 10, the trigger 11 overflow, block 12 capture line, the element NOT 13, the first, second blocks 14 and 15 address generation, block 16 comparison, trigger 17 applications, trigger 18 busy, output 19, information input 20, groups of clock inputs 21 and 22, input 23 ready to transmit, input 24 blocking the trunk, information output 25, output 26 request and transmission, address output 27, output 28 blocking the highway, the input-output 29 of the capture of the highway.

The analyzer of the combination of the boundary code contains the element-OR-NOT 30, the counter 31, the element AND 32, the clock inputs 33, the information input 34, the enabling input 35 ,.

The address generation blocks 14 and 15 contain an address counter 36, a multiplexer 37, a control output 38, a clock input 39, a setup input 40,

Blrk 3 contains the element NOT 41, the logical switch 42, the element IS-NOT 43, the information input 44, the control inputs 45 and 46, the information input 47, a group of outputs 48,

In FIG. 6, the proposed device is designated 49.

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The device serves for buffer storage of a message coming from a source of information intended for transmission over a communication channel.

Each message is limited to opening and closing flags, which represent a combination of the form 01111110. The combination between the opening and closing flags is code independent due to the use of bit stuffing in the source of information and cannot contain more than 5 contiguous single bits,

After the opening flag follows the address of the recipient of information. A group of identical devices connects-. with a common highway connected to the source of information. The identification of the message intended for this device is made at the recipient address. The connection of devices of the highway is shown in FIG. 6,

As the block 12 capture line you can use a multi-channel priority device (one channel in each device 49 in Fig, 6),

The device works as follows

In the initial state, counter 8 and all triggers are reset. Information information input 20 is received in a sequential form. messages, each of which is intended to the corresponding device 49 (FIG. 6). .

The group of clock inputs 21 receive pulse sequences that are synchronous with the information signals acting on input 20. The group of clock inputs 22 receive sequences of pulses with a transmission frequency over the communication channel. Information is written to the memory unit by signals acting on inputs 21, and reading by signals acting on inputs 22. Switching clock sequences from write mode to reading mode is performed using switching unit 3 (FIG. 4). Switching is performed by signals acting via control inputs 15 and 46 of block 3. Simultaneously with the switching of clock signals, block 3 produces sub0

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The output 34 is connected to the device input 20 or to the output of memory block 6. In the absence of an active signal at inputs 45 and 46 at the outputs of block 3, the signals do not act,

In the initial state, both control inputs 45 and 46 have zero signals. The zero signal at the inverse control input 45 connects the group of outputs 48 of unit 3 to the group of inputs 21 of the device, and the information output (input 34 of unit 7) to the information input 20 of the device.

The writing and reading of information in the memory block 6 is performed bit by bit. The address of the cell is determined by the state of counter 2. Until the trigger 18 is cleared, for each zero bit on the information input 20, the OR-NO 1 element (performing the function of the IS-NOT element in negative logic) is triggered and resets the 2-address counter memory (the element OR NOT 1 is gated by the signal from the input 21. Fig. 5).

Analyzer 7 analyzes the sequence of bits received by po information input 20, selects the combination of the flag (01111110), to which the message begins.

The analyzer 7 operates as follows.

The input 33.1 to the counting input of the counter 31 receives clock pulses (output 48.1 of block 3). At input 32.2, a sequence of pulses is output from output 48.3 of block 3. When a zero bit arrives at the device 20 input, or a zero signal acts at input 34 of block 7, counter 31 is reset from the OR-NOT element 30. And the 32 element connected to the output of counter 31 and playing the role of the decoder of the number 6, it works after the input 34 receives another six information 1, i.e. flag combination (the last, 8th, flag bit is not taken into account, since the source of information cannot form combinations containing order seven 1), the signal from the output of the AND 32 element allows the counter to work, the counting input of which is also as at input 33.1 of the analyzer 7, the clock sequence comes from

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yes 48.1 of block 3. At the next clock interval, the counter triggers and at the output of its 1st bit a signal 1 is generated, which is fed to the input 35 of the analyzer 7 and prohibits further reset of the counter 31, Thus, the signal at the output of the And 32 element has two periods clock frequency (state 6 and 7 of counter 31). This signal sets to; 1 trigger 18, prohibiting further reset of counter 2 from the element OR NOT 1.

Counter 8 also counts two pulses, with the result that the output of its second bit is set to 1. The signal from the output of the first bit. counter 8, the current one period of the clock frequency starts block 14 address generation.

Block 14 address generation works as follows.

In the initial state, the output of the last digit of counter 36 is a signal with a level 1, which prohibits counting at input C. with the address inputs of the multiplexer 37, inputs XI-X8 are connected in series to the output of the block t4, to which signals of address setting of this device are given. As a result, a reference byte is generated in output 41 in a sequential form. addresses of the device with which block 16 compares the address byte of the message following the flag byte. After the eight bits of the address have been output, 1 is output at the 4th bit of the output of counter 36, which blocks the counter in state 0001,

If any message bit does not match the corresponding device address bit, a pulse occurs at the output of block 16, which, on the C input, resets the trigger 18, bringing the device back to its initial state. (For the comparison block 16, the EXCLUSIVE OR element is used, the output of which is gated by a signal from the output 47.3 of block 3). .

If the address of the message coincides with the reference address of the device, trigger 18 remains in state 1, the counter is not reset, and a message is displayed.

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The memory is bitwise written into consecutive cells of memory block 6.

When a second (closing) message appears, the analyzer 7 is triggered again, causing the third discharge of counter 8 to 1 (the resulting pulse on the first output of counter 8 starts block 14 again, but the trigger 18 cannot be reset by C input, since its D-input is valid 1).

At input 45 of block 3, level 1 is set, as a result of which switching unit 3 closes and stops passing signals to the outputs. At the same time, a signal is removed from the reset input of the trigger 4, which holds it in the CONDITION O, and from the output 26 of the device to the computer a signal is sent to the transmission request. At the same time, the element AND 9 opens, which resets the counter 2 memory addresses, preparing the device for reading information from block 6.

In response to the transmission request from the computer, input 23 receives a ready-to-transmit signal, on the front of which trigger 4 is set to state 1, and closes element 9. At the same time, the signal with level 1 is fed to input 46 of unit 3, which connects group 48 of outputs A group of device inputs 22, and an output 34 - to the output of block 6. The clock signals received by a group of outputs 49 are used to read block 6 of memory (48.2) and simultaneously increment counter 2 (after the decay of the output 48.1).

The message read from block 6 enters the computer via information output 25.

After the output of block 6 will be decrypted the 2nd flag, i.e. after the entire message has been removed from the memory and transmitted to the communication channel, the fourth digit of the counter 8 goes to state 1, as a result of which the triggers 11 and 17. are set. The latter resets three; the gauge 18, which in turn sets in About counter 8 and trigger 11.

From the output of trigger 16 to the input of block 12 for capturing the trunk, a signal is received for transmitting a receipt for freeing memory to the source of information. If this mouth

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The device is allowed to output information to the highway (the blocking signal at output 27 is absent), block 12 produces a capture of the trunk, sets a blocking signal at output 28 and a signal to capture the highway at the input-output 29. Prohibiting other devices from connecting to the highway. Simultaneously, a signal is formed at the resolving output of block 12, as a result of which the potential of level 1 is removed from the input 40 of the address generation block 15. At output 42 of block 15, an address code for this device is generated. The operation of block 15 is similar to the operation of block 14.

The address code through the trunk amplifier 10 is fed to the information output 27.

After outputting the eight bits of the address at output 44 of block 14, a signal arises, on the front of which a flip-flop 16 is reset, the drive device is reset.

If while writing or reading the memory, the second flag is not detected (the flag code is distorted as a result of interference or the length of the message exceeds the memory capacity) during transmission

The completion of counter 2, trigger 11, is set to 1 via a dynamic input, the circuit is reset, and an address code is sent to information output 27, indicating that the memory is free and the source can enter another message.

Claims (2)

1. A device for interfacing an information source with a communication channel, comprising a memory block, a boundary code combination analyzer and a switching block, characterized in that, in order to extend the functionality by transmitting a source of information to the source of a free memory receipt in code form, an OR-NOT element, a memory address counter, a transmission trigger, a control counter, an OR element, an AND element, a bus driver, an overflow trigger, a line capture block, an NOT element, the first and second address generation blocks , comparison block, trigger for wkI, trigger trigger, and the output Sh five 20 25 I1310829 the first bit of the control counter is connected to the enable input of the analyzer of the boundary code combination and to the installation input of the first address generation unit, the output of which 5 is connected to the first information input of the comparison unit, the second information input of which is connected to the first input of the OR-NOT element, ; the first information input of the switching unit and the input of the device for connecting the information output of the information source; the second input of the OR element is NOT connected to the single output of the busy trigger, the zero output of which is connected to the reset inputs of the control counter and the overflow trigger, the single input of which is connected to the output the fourth bit of the control counter, the output of the third bit of which is connected to the input of the mode of the memory block, with the input of the prohibition of the switching unit, with the zero input of the transmission trigger, with the first input And, with the information entry of the trigger trigger, with the device input for connecting the transmission request input, the single input of the trigger trigger is connected to the input  the resolution of the control counter and the analyzer output, the boundary code combination, the clock input of the occupation trigger is connected to the output of the comparison unit, the zero input of the occupation trigger is connected to the output of the trigger trigger and to the input of the capture block request — the highway block output and the output of the highway capture which are connected respectively with the device outputs for connecting the computer trunk interlock input and with the device input / output for connecting the computer main input I / O, the highway blocking input the line capture unit is connected to the input of the device to connect the output of the computer line lockout; the output output of the exchange of the line capture unit is NOT connected to the installation input of the second unit ; address generation, whose information output through the bus generator is connected to the output of the device  VA for connecting the address input of the computer, the synchronization output of the address generation block is connected to the dynamic thirty 35 40 45 50 .-55 i vkho toto ra sablo e ko u k s te o s cyto ti ad hedny adi for ty mi me ad i pa on the edge of the pack you ko el pr not ho ra ra and that shchi Sh five 20 25 5 30 35 40 45 50 55 the trigger input of an application whose single input is connected to the overflow trigger output, the dynamic input of which is connected to the output of the last bit of the memory address counter, the reset input of which is connected to the output of the OR element, the first and second inputs of which are connected respectively to the outputs of the SH-N and And, the second input of the element And is connected to the zero output of the transmission trigger, the dynamic input of which is connected to the input of the device for connecting the output of the readiness to transmission, the single output of the transmission trigger is connected to in The resolution of the switching unit, the second information input of which is connected to the information output of the memory block and the output of the device for connecting the information input, the address inputs of the memory block are connected to the information outputs of the memory address counter, the group of inputs of the device for connecting the first group of clock outputs of the information source is connected with the third input of the element OR NOT, with the clock inputs of the first and second blocks of address generation and with the first group of clock inputs of the switching unit, the second groups and clock inputs of which are connected to a group of device inputs for connecting to the second group of clock outputs of the information source, the group of outputs of the switching unit is connected to the counting inputs of the control counter and the memory address counter, with gating inputs of the memory block and the comparison unit and clock inputs of the boundary analyzer the code, the information input of which is connected to the output of the switching unit, 2. The device according to claim 1, of which is that the analyzer of the combination of the boundary code contains the element OR NOT, the counter and the element AND, the output of the element OR NOT connected to the reset input of the counter The outputs of two bits of which are connected to the output of the decoder through the AND element, the counting input of the counter and the first input of the OR-NOT element form the clock inputs of the analyzer, the second and third inputs of the OR-NOT element are the information and enabling inputs of the analyzer. 20J one . 0., G Editor M.Dish Compiled by S. Buruhin Tekhred L.Oleynik Proofreader L. Patay Order 1893/46 Circulation 673 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing company, Uzhgorod, st. Project, 4 FIG. five FIG. five