GB2129657A - Circuit arrangement for transmitting digital signals in a communication system, particularly in a PCM telephone private branch exchange - Google Patents

Abstract

If, in a digital communication system, e.g., a PCM private branch exchange, signal bits are transferred between two functional units, delays may occur on the transmission lines (üL) and in the gates (LE1) and cause switching errors. To eliminate the need to adjust the delays in each exchange by special delay elements, a compensating circuit (AGL) containing several multiple D flip-flops (FF1, ..., FF4) is provided at the receiving end. The writing and reading of the signal bits into and from the flip-flops is controlled by two shift registers (SR1, SR2) which are clocked by the transmitting clock and the receiving clock, respectively, and are placed in a defined output state by the respective frame synchronization pulses. Delay compensation is thus performed automatically. <IMAGE>

Description

SPECIFICATION Circuit arrangement for transmiffing digital signals in a communication system, particularly in a PCM telephone private branch exchange The present invention relates to a circuit arrange mentfortransmitting digital signalsforinstance in a telecommunication system.

In a known arrangement, two telecommunication exchanges are interconnected via a PCM four-wire circuit. Atthe receiving end of each pair of wires, there is a buffer used as a compensating circuit. Ifthe exchanges run atfrequenciesthat are independent of each other, the buffers are needed astheswitching networkcontroloperatesattheclock rate of its own exchange, and so can only process incoming speech samples which are in phase with this clock. The buffers are also needed if the two exchanges operate synchronously, as variations in the phase of the incoming signals due to changes in delay must be compensated for.

Compensation for signal-propagation times may also be needed within atelephone exchange such as a PABX in which digital signals, e.g., PCM speech samples or data, aretransferred betweentwo separated functional units or modules, although both such units are supplied with clock pulses from a master clock, so that, in theory, the two functional units are synchronous. Such units are, for example, switching networks in different racks ofthe exchange. The functional units may contain line circuits, junctors, and additional facilities.

In known circuits, gate delays and delays due to different line lengths must be compensated for by a delay adjustment using special delay elements. For each system or exchange, a new adjustment must be performed.

An object ofthe invention isto provide a circuit arrangementwhich eliminates the need for such adjustment work.

According tothe invention,there is provided an arrangementfortransmitting digital signals in a communication system, including two functional units which exchange the signals and are interconnected by two transmission lines onefor each direction and each said line housing a compensating circuit at its receiving end, wherein the compensating circuit includes several stores whose data inputs are fed with the signal bits arriving in parallel from the transmitting unit, and whose data outputs are connected to the internal signal line ofthe receiving functional unit,whereinthedatainputsofthestores are clocked by a first shift register clocked at the clock rate ofthe transmitting unit, and wherein the data outputs ofthe stores are enabled by a second shift register clocked at the clock rate ofthe receiving unit.

The main advantages ofthe invention arethatthe delay ofthe transmitted signals can be compensated for with a small numberof Dflip-flops and avery simple circuitfor synchronizing and controlling these flip-flops. It eliminates the need to perform different adjustments depending on the type of exchange.

An embodiment of the invention will now be explained with reference to the accompanying drawings, in which: Fig. 1 shows two functionatunits interconnected by atransmission line in a system using an arrangement embodying the invention; Fig. 2 shows the arrangement embodying the invention used in the system of Fig. 1; Fig. 3 is a timing diagram forthe arrangement of Fig.

2 if there are no signal delays onthetransmission path, and Fig. 4 shows a corresponding timing diagram if signal delays occur on the transmission path.

Fig. 1 showstwofunctional units M1 and M2 of a PCM exchange of modular construction, which units (hereinafter called "modules") are interconnected by a transmission line (iL in the form of an 8-bit data bus overwhich the digitally encoded speech signals or data aretransmitted in parallel. Forsimplidty, onlythe data bus from the module M1 to the module M2 is shown; a similar data bus runsfrom M2to Ml.

A master clockZTG is connected to a clock-pulse receiver and distributorTEV in the module M1 and to a clock-pulse receiver and distributorTEV* in the module M2, sothatthe subcircuits of the two modules are supplied with the same clock pulses and hence are at least in principle, synchronous.

The module M1 contains a transmitting memory SSPforthesignalsto be transmitted, an address register SAS holding the addresses ofthe respective memory locations, and a transmitting buffer SZS containing a number of parallel flip-flops. If each speech sample is encoded into an 8-bit codeword, the bufferSZS has 8flip-flops, and the line üL8 individual wires.

In the module M2,which representsthe receiving unitforthe direction oftransmission shown, the line üLterminates in a compensating circuitAGL, which will be described with the aid of Fig. 2. From this circuit, the speech signals pass to a receiving memory ESP, controlled by an address register EAS. The clock-pulse receiver and distributorTEV* receives the clock pulses from the master clock ZTG and supplies the individual parts ofthe module M2 with the necessary clock pulses.

The receiver and distributorTEVofthe module M1 suppliesthetransmitting buffer SZS and the compensating circuitAGLwith frame synchronization signals over a line RS and with transmitting clock signals over a line ST. Both the line island the transmitting and receiving devices are also presentforthe opposite direction oftransmissionfrom M2to M1, but are not shown.

Each PCM signal is sent as eight parallel bits over the line üL using TDM with a frame duration of 125 usec. Theframe is divided into 51 2time slots, so that a time slot, in which one speech sample or one data bit is sent, is 244 ns long.

If information isto besentfrom M1 to M2,for example, a cell x inthetransmitting memory SSP and a cell yin the receiving memory ESP are addressed by the adress registers SAS and EAS, respectively. The data in the cell with the addressx is read, placed onto the line üL, and written into the receiving-memory cell with the address. The memories SSP and ESP have capacities of, e.g., 512 locations, i.e., they can store one frame.

While sending the signals from M1 to M2, problems may arise due to gate delays and to propagation time delays on lines of different length. The gate delays, particularly in the line drivers needed for transmission over the bus üL,andthe propagation time delays may cause switching errors. To avoid such errors, the total transmission delay must be below 244 ns. If the delay is longer, signals forthe receiving-memory cell y will be written into the receiving-memory cell y+ 1. Under unfavourable conditions, however, delays may occur which amountto a multiple of 244 ns.The factthat delays occur presents no major problem because a delay which is constantfor different installations- e.g. a delay of one time slots can be easily compensatedfor by arranging thatthe address register SAS addressesthe memory cellxone time slot earlier, so that the transmitted data reaches the memory ESP in M2 precisely atthe correcttime.

The problem is that, in switching systems of different design, different delays may occur even if circuit boards ofthe same kind are used. It would be possible to augmentthetotal delayto obtain a preset value-preferably a multiple of244ns-e.g. using additional, adjustable delay elements. Such a con stantdelayforall designsofthesystem could then be compensated for by the aforementioned advance addressing of the transmitting memory by its address register. This, however, would necessitate measuring the delayforeach newtype of exchange, and then adjusting the individual delay elements.Such a considerable expenditure is avoided by the arrange ment embodying the invention, which compensates fordifferentsignal delays automatically without requiring any measurements. By suitable design, all delays occurring in practice can be compensated for.

With the compensating circuit AG L, Fig. 2, delays of uptothreetimeslots, inthiscase3 x 244ns = 732 ns, can be compensated for. The line ill is connected to a line receiver circuit LE1 containing 8 parallel line receivers. The outputs of these receivers are connectedtothe inputs DATA IN of 4 parallel D flip4lops, FF1, FF2, FF3 and FF4 via an internal bus IBI. These D flip-flops are eight-elementflip4lops, and theirtristate outputs DATA OUT are connected to the receiving memory ESP (see Fig. 1) by an internal bus IBO.The lines RS and ST, which transmittheframe sync signals and the transmitting clock, respectively, are connected to a second line receiver circuit LE2, which contains two line receivers. The outputs of these receivers are connected to a switching input LD and a clock input CL, respectively, ofafirstshift registerSRi.The clock input CL controls the writing into the Dflip-flops FF1 to FF4 of the signals arriving on thetransmission line (iL. To this end, the parallel data outputs QA, QB, Oc, and OD of SR1 are connected to the clock inputs CL of FF1 to FF4 via clock lines S1,S2, S3, and S4, respectively.At the data input SR1,a logic "1" is applied, while its other data inputs B, C, and D are at a potential corresponding to logic "0". The output QD of SR1 is fed backto a serial input SI.

Depending on the logic level applied atthe switching input LD, eitherthe data present at the data inputs A to D is transferred into SR1 (or SR2) or the transferred data isshifted around in circularfashion.

The reading of data from FF1 to FF4 is controlled by a second shift register SR2, whose outputs QAto QD are connected to the read enable inputs OUT EN of FF1 to FF4via read control lines L1 to L4. In SR2 also, the output QD is fed backto the serial input SI, while the frame sync pulses and the read pulses of the module M2 are applied over lines RS* and ST* to the switching input LD and the clock input CL, respectively. Here the "1" state is applied atthe data input B, while the other inputs A, C,and D are at logic "0".

The registers SR1 and SR2 are so loaded bythe frame sync pulses arriving at their switching inputs LD thatthe next signals on the line üL is written into the first D flip-flop FF1, and that data in the second D flip-flop FF2 is read and transferred overthe internal bus IBO to the receiving memory ESP.

Since SR1 is controlled at the transmit clock rate of the module M1, SR1 and, hence one ofthe Dflip-flops FF1 to FF4 is clocked only if data is coming in overthe line üL.

The operation ofthe arrangement of Fig. 2 when the data from M1 to M2 is not delayed is apparentfrom the pulse graphs of Fig. 3.

Thefirstthree lines Z1, Z2 and Z3 relate to the transmitting process in the module M1. Line Z1 shows the frame syne sig nal, and line Z2 shows the transmitting clockofMl,transmissiontaking place on the leading edge of each clock pulse. In the present case, the clock signal has a frequency of 4.096 MHZ.

Line Z3 gives the receiving-memory addresses for which the 8-bit signals or data transmitted by the module M1 are intended.

Lines Z4to Z7 show the operations while receiving the signals in M2. Line Z4 shows the frame sync signal arriving from the module M1 at SR1 of M2. LineZ5 shows the transmitting clock arriving at SRl,which is clocked on the trailing edge. In linesZ6 and Z7, the D flip-flop into which data is written and the receivingmemory address for which this data is intended have been set off.

The operations during the reading ofthe data received in M2 and contained in the D flip4lops FF1 to FF4 are apparentfrom lines Z8 to Z1 1. Line Z8 shows the frame syne signal of M2, and line 9showsthe read signal for SR2,the reading being enabled by the trailing edge. In lines Z10 and Z1 1,the D flip-flops from which data is read in the module M2 andthe receiving-memory addresses for which this data is intended have been set off. After arrival oftheframe sync pulse,the dataforthe receiving-memory address 3 is thus entered into the Dflip-flop FF1, and the data forthe receiving-memoryaddress 0 os readfrom the Dflip-flop FF2 (1). Three clock pulses later, the data for the receiving-memory address 3 is read from FF1 (2).

Fig. 4 illustrates the corresponding operations if a delay of two time slots, i.e., of 488 ns, occurs between the transmission ofthe signals in M 1 and the reception thereof in M2.

Lines Z1 to Z3 relate to the transmission of the signals by M1; lines Z4to Z7 relate to the reception of the signals at M2, and lines Z8to Z11 relate to the reading from the D flip-flops in the compensating circuitAGL ofthe signals received in M2.

The waveforms, D flip-flops, and receiving-memory addresses shown in lines Z1 to ZI 1 relate to the same operations as those illustrated by lines Z1 to Z1 7 of Fig.

3. Fig. 4shows that already one clock pulse afterthe data forthe receiving-memory address was written into the Dflip-flop FF1-cf.(l)-, this data is read out again-(2). If the delay between M 1 and M2 was three time slots, difficulties would probably occur, because the data forthe receiving-memory address 3would have to be written into and read from the D flip-flop FF1 simultaneously, i.e., the read pointer would have practically caught up with the write pointer. These difficulties can be easily avoided by adding a fifth D flip-floptothe compensating circuitAGL, in which case the two shift registers SR1 and SR2 must each have one additional output.

Such an arrangement also works, of course, if the delays do not amount to an integral multiple of one time-slot period, i.e., of 244 ns.

Claims (7)

CLAIMS:

1. An arrangementfortransmitting digital signals in a communication system, including two functional units which exchange the signals and are interconnected by two transmission lines (ijL) oneforeach direction and each said line, housing a compensating circuit at its receiving end, wherein the compensating circuit (AGL) includes several stores (FF1 ..., ..., FF4) whose dats inputs (DATA IN) are fed with the signal bits arriving in parallel from the transmitting unit (M1), and whose data outputs (data out) are connected to the internal signal line (IB) ofthe receiving functional unit (M2) wherein the data inputs of the stores are clocked by a first shift register (SR1 ) clocked at the clock rate of the transmitting unit (M1 ), and wherein the data outputs ofthe stores are enabled by a second shift register (SR2) clocked at the clock rate of the receiving unit (M2).

2. An arrangement as claimed in claim 1,wherein each said store is a set of parallel arranged Dflip-flops one perwire of the transmitting line.

3. An arrangement as claimed in claim 2, wherein the shift registers (SR1, SR2) are circulating registers having parallel outputs (GA 0B QC, GD) connected to the clock inputs (CL) and the read enable inputs (OUT EN), respectively, ofthe Dflip-flops (FF1,..., FF4).

4. An arrangement as claimed in claim 2 or 3, wherein the clock ofthe transmitting unit (Mi) is applied to the clock input (CL) of the first shift register (SR1), and the clock ofthe receiving unit (M2) is appled totheclock input (CL) of the second shift register (SR2).

5. An arrangement as claimed in any one ofthe preceding claims, wherein the first shift register (SR1 ) has a switching input (LD) to which the frame synchronization signals from the transmitting unit (M1) are applied, and the second shift register (SR2) has a switching input (LD) to which the frame synchronization signals from the receiving unit(M2) are applied.

6. A circuit arrangement as claimed in any one of the preceding claims, wherein the data inputs (A, B, C, D) ofthe first and second shift registers (SR1, SR2) are so wired that the signals from the transmitting unit (M1) are transmitted n time slots before being read from the compensating circuit (AGL) in the receiving unit (M2), and that n is not greater than the number of stores minus one.

7. A circuit arrangement for compensating for delays in transmission between two functional units, e.g. in a TDM-PCM-PABX, substantially as described with reference to the accompanying drawings.