GB2228848A

GB2228848A - A data synchronisation arrangement

Info

Publication number: GB2228848A
Application number: GB8828671A
Authority: GB
Inventors: Andrew James Pickering
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-12-08
Filing date: 1988-12-08
Publication date: 1990-09-05
Also published as: GB8828671D0

Abstract

The data synchronisation arrangement comprises at least four stages 4a-4d connected to a common asynchronous data input line and a common synchronous data output line. Each stage includes a register comprising two flip-flops (Fig. 5). One flip-flop (7) stores data information and the other (6) stores write and read flag signals. The registers are arranged as a ring buffer and is used for the input of asynchronous data into a synchronous system. The arrangement eliminates timing problems between data DCK and system MCK clocks. A set of rings each controlled as a whole by a frame packet marker for synchronisation of data packets. A ring may provide immunity to jitter or frequency variation, or a variable delay FIFO, the delay being determined by the initial state of the ring. <IMAGE>

Description

A DATA SYNCHRONISATION ARRANGEMENT The present invention relates to a data synchronisation arrangement for use in digital communications systems which handle asynchronous data.

An increasingly common requirement of digital communications systems is the ability to receive asynchronous data input signals.

The asynchronous data must then be synchronised with the system reference clock to allow sychronous operation.

The kind of situation where the use of this arrangement is envisaged is illustrated in Figure 1.

One or more asynchronous data inputs may be fed into a system 3 operating on a single master clock, MCK. From each data input stream a data clock signal, DCK, is extracted by circuits 1 which are used to clock the input data into the DATA SYNC blocks 2. The master clock MCK is then used to clock the data sychronously into the system. Many techniques for extracting a clock signal from a digital data stream already exist and they will not be discussed further. The signals presented to the DATA SYNC block 2 are illustrated in Figure 2. Since the data clock DCK and master clock MCK are asynchronous there is no fixed phase relationship between the ts o. Hence the master clock MCK cannot be used to clock the data into the system 3 since the clocking edge may occur on a data transient causing a potential error, and this presents a problem.

The solution to this problem is to queue the input data bits such that the data being read by the master clock MCK at any time is held static. Data is then read from the head of the queue whilst new bits are added at the back end of the queue.

Accordingly, an object of the present invention is to provide a data synchronisation arrangement which overcomes the problem in an effective manner.

According to the present invention there is provided a data synchronisation arrangement comprising at least four stages connected to a common asynchronous data input line and a common synchronous data output line, each stage includes a register in which data bits are stored, and is arranged with means to generate a flag signal to indicate that the register is ready for a read or write operation.

An embodiment of the present invention sill now be described with reference to the accompanying drawings in which: Figure 1 shows a typical data transmission system in which the invention may be used; Figure 2 show the data and clock signals used in such a system; Figure 3 show a synchronisation arrangement according to the present invention; Figure 4 shows the signals used by the arrangement of Figure 3 for register operations; and, Figure 5 shows the implementation of a register stage shown in Figure 3.

Referring to Figure 3, the synchronisation arrangement is shown in the form of a ring buffer. This consists of a set of registers 4a to 4d which are used to stored the data bits and flag whether the bits are ready for a read or write operation. Simple combinational logic 5 is used to select the next read register and write register at the front and back end of the queue respectively. There are a number of ways to implement the ring buffer registers as will be described later.The input and output signals going to each ring buffer register 4a to 4d are as follows: INPUTS RE - Read Enable WE - Write Enable DCK - Data Clock DIN Data Input OE - Output Enable OUTPUTS DO - Data Output (Tristate Output) RA - Readable State (Complement of WA) WA - Writeable State (Complement of RA) The operation of the ring buffer register will now be described with reference to Figures 3 and 4.

If the register 4a, for example, is write enabled then the rising edge of the data clock DCK will write the input data into the register, the falling edge of the data clock DCK then sets the register into readable mode.

If the register 4a is read enabled then the rising edge of the master clock MCK or input OE will gate the data stored in the register onto the data output line; the falling edge of the master clock MCK or input OE then sets the register into writeable mode.

The arrangement of Figure 3 should be arranged such that an initial state is obtained with two adjacent registers (say registers 4a and 4b) being in a writeable state (WA high, RA low) and the other two registers (4c and 4d) being in a readable state (RA high, WA low). In this initial state the decoding logic is such that register 4a is write-enabled (WE high) and register 4c is read-enabled (RE high), with the other registers disabled.

A data write cycle may now occur such that the rising edge of the data clock DCK signal writes valid input data into the writeenabled register 4a. After the data is written, the falling edge of data clock DCK flips register 4a into a readable state. The decoding logic then selects register 4b as write-enabled.

Meanwhile, a data read cycle may be occurring such that the rising edge of the master clock MCK signal gates the data stored in the read-enabled register 4c onto the data output lines. After the data has been accessed, the falling master clock MCK edge flips register 4c into a writeable state. The decoding logic then selects register 4b as read-enabled.

The read and write operations occur continuously, thus cycling the read-selected and write-selected registers round the buffer ring.

Because the read and write operations are being carried out on different registers at any one time, no timing constraints are imposed between the data clock DCK and the master clock MCK signals. Thus a purely asynchronous data input system is achieved.

Referring to Figure 5, one possible implementation of a single ring buffer register is shown, e.g. 4a. One +ve edge-triggered masterslave flip-flop 6 and one -ve edge-triggered master-slave flip-flop 7 are used to store the data and latch state respectively. The data clock DCK and master clock MCK signals which effect the write and read operations are gated by the write-enabled and read-enable RE inputs, by way of gates 8, 9, 10. Flip-flop 7 generates the readable and writeable signals RA, WA respectively. The data output from flip-flop 6 is outputted by way of circuit 11, under the control of the output from gate 8.

The above embodiment has been of one example and is not limited thereto. It consists of only four stages which is the minimum that can be used for completely asynchronous operation. However, since each stage is identical the size of the ring can be increased and is only limited by practical constraints. A large ring may be therefore be used where a great immunity to data jitter or frequency variation is required.

Another use of the ring buffer is synchronisation of the data packets whereby several rings are initialised and data is written into the ring only after a frame packet marker for that input has been detected. Reading from all of the buffers is delayed until all of the frame markers have been detected. The output data frames are thus synchronised.

One further use of the ring buffer is as a variable delay length FIFO whereby the input-output delay is determined by the initial state of the registers in the ring.

Claims

CLAIMS:

1. A data synchronisation arrangement comprising at least four stages connected to a common asynchronous data input line and a common synchronous data output line, each stage includes a register in which data bits are stored, and is arranged with means to generate a flag signal to indicate that the register is ready for read or write operation.

2. An arrangement as claimed in claim 1, wherein each register includes two flip-flops, one of which is arranged to store the data, and the other is arranged to store information relating to the flag signals.

3. An arrangement as claimed in claim 2, wherein each register is provided with a read enable input connected to receive a read enable signal generated by a gate circuit, dedicated to that register, said gate circuit having first and second inputs, the first input is connected to receive a read flag signal from the register to which it is dedicated, and the second input is connected to receive a read flag signal from a different register.

4. An arrangement as claimed in claim 2 or 3. wherein each register is provided with a write enable input connected to receive a write enable signal generated by a gate circuit dedicated to that register, said gate circuit having first and second inputs, the first input is connected to receive a write flag signal from the register to which it is dedicated, and the second input is connected to receive a write flag signal from a different register.

5. An arrangement as claimed in claim 4, wherein the flag signals received from the different registers are inverted at the second inputs of the gate circuits.

6. An arrangement substantially as hereinbefore described.

7. An arrangement substantially as hereinbefore described with reference to Figures 1 to 5 of the accompanying drawings.