JPS56111350A - Error control system - Google Patents

Error control system

Info

Publication number
JPS56111350A
JPS56111350A JP1410380A JP1410380A JPS56111350A JP S56111350 A JPS56111350 A JP S56111350A JP 1410380 A JP1410380 A JP 1410380A JP 1410380 A JP1410380 A JP 1410380A JP S56111350 A JPS56111350 A JP S56111350A
Authority
JP
Japan
Prior art keywords
register
synchronizing
signal
interleaving
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1410380A
Other languages
Japanese (ja)
Inventor
Eiichiro Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1410380A priority Critical patent/JPS56111350A/en
Publication of JPS56111350A publication Critical patent/JPS56111350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Abstract

PURPOSE:To enable to send all data blocks by successively shifting readout positions of respective codes synchronizing with the readout timing of data when data blocks stored for bit interleaving is read out. CONSTITUTION:A BCH code of 15-bit length supplied from the signal input terminal is converted by register 2 into a parallel signal, which is supplied to the interleading register (15X127 bits) 3 in parallel synchronizing with a synchronizing signal from synchronizing signal generator 6. On the other hand, registers 4 and 5 set the addresses of interleaving register 3. When the signal from signal input terminal 1 is read in this interleaving register 3, 127 words of the information of 15-bit length are stored in parallel and on the storage, the information stored in register 3 is outputted to terminal 7. When the data are read out, address setting registers 4 and 5 operate at the same timing synchronizing with the synchronizing signal from circuit 6, and the contents of register 3 are outputted slantingly to terminal 7.
JP1410380A 1980-02-06 1980-02-06 Error control system Pending JPS56111350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1410380A JPS56111350A (en) 1980-02-06 1980-02-06 Error control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1410380A JPS56111350A (en) 1980-02-06 1980-02-06 Error control system

Publications (1)

Publication Number Publication Date
JPS56111350A true JPS56111350A (en) 1981-09-03

Family

ID=11851779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1410380A Pending JPS56111350A (en) 1980-02-06 1980-02-06 Error control system

Country Status (1)

Country Link
JP (1) JPS56111350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03118640A (en) * 1989-07-06 1991-05-21 Digital Equip Corp <Dec> Fault admission memory
JPH0834444B2 (en) * 1985-03-04 1996-03-29 ブリティシュ・テレコミュニケ−ションズ・パブリック・リミテッド・カンパニ Encoding transmission method and apparatus, code receiving method and apparatus, encoding method and apparatus, and decoding method and apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0834444B2 (en) * 1985-03-04 1996-03-29 ブリティシュ・テレコミュニケ−ションズ・パブリック・リミテッド・カンパニ Encoding transmission method and apparatus, code receiving method and apparatus, encoding method and apparatus, and decoding method and apparatus
JPH03118640A (en) * 1989-07-06 1991-05-21 Digital Equip Corp <Dec> Fault admission memory

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