JPS5931740B2 - Storage device control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a main memory device consisting of a plurality of pages when a predetermined amount of memory is one page, and in particular to a method for controlling a main memory device composed of a plurality of pages when a predetermined amount of memory is one page. This invention relates to simultaneous writing and its response signal reception method.

Conventionally, there has been no system that allows software to specify and control access to multiple pages in any combination of a main memory device consisting of multiple pages.

However, in online systems such as small and medium-sized electronic exchange systems, the need for the above functions is increasing. in general,
In electronic switching systems for small and medium-sized offices, the amount of programs and data is large, so only frequently used program modules and data are stored in the main memory. Programs and data other than those mentioned above are stored in the secondary storage device, and are read out and used in an overlay area provided in the main storage device as needed. In this case, what is read from the secondary storage device includes program modules and data groups, and on the secondary storage device,
Program modules and data are stored in a continuous fixed capacity for each functional unit in relation to the existing program structure and for ease of maintenance of large-scale software. On the other hand, in a main memory device consisting of multiple pages, the instruction execution time of the central processing unit is shortened by separating the pages in which programs are stored and the pages in which data is stored, and by overlapping instruction fetches and operand fetches. It is possible to do so.

However, if the above-mentioned overlay method is adopted in a system that stores programs and data in separate pages, an input/output command, that is, a secondary memory read command is generated first, a program module is read into the program page, and then a A secondary storage read command is generated again and the data group is read into the data page, resulting in a decrease in processing performance. An object of the present invention is to provide a storage device control method that can speed up overlay processing by enabling simultaneous writing to arbitrary multiple pages. Another object of the present invention is to provide a storage device control method that allows simultaneous access to multiple pages even if the pages have different speeds.

Still another object of the present invention is to provide a control system that can receive and process response signals even if any of the pages are not implemented.

The storage device control method of the present invention provides a data processing system having a main storage device made up of a plurality of pages and a storage device control unit that controls the main storage device, in which each of the main storage devices made up of the plurality of pages is The access times of the pages are different speeds, and the storage device control unit includes means for receiving access response signals from each page of the main storage device, and means for detecting an unimplemented page in the main storage device; When an access to an unimplemented page is detected, the access response receiving means for the page is set to an access response receiving state within a predetermined time, and when multiple pages are simultaneously accessed, all access response signals from the accessed multiple pages are received. and means for generating an access response reception completion signal at a time point. Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and a storage device 10 is composed of four pages 11, 12, 13, and 14. The storage device control unit 20 includes a page access control circuit 30 and a page access response signal reception control circuit 40. 21 is a data bus, which is connected to the storage device control unit 2 for address transmission and data transmission/reception.
0 and each page 11, 12, 13, and 14 are commonly connected.

31, 32, 33, 34 are pages 11, 12, respectively.
13 and 14, and its command is issued from the page access control circuit 30.

41, 42, 43, and 44 are response signals to the page access request signal lines 31, 32, 33, and 34, respectively, and are received by the page access response signal reception control circuit 40 from each page.

Since this embodiment employs a different speed memory control method, the response time to a page access request may be different between pages. Reference numerals 46, 4r, 48, and 49 are mounting display lines of the corresponding page, which are "1" when mounted and "0" when not mounted.

These implementation information are also input to the page access response signal reception control circuit 40 and used to control the creation of the access response signal. Figure 2 shows the page access control circuit 3 in Figure 1.
FIG.

Reference numerals 61 and 62 are page registers in the central control device, which are switched by a switching circuit 65 so that 61 is used during an instruction fetch and 62 is used during an operand fetch.

The contents of the switched page register are expanded by decoder γ0, and any one of Tl, r2, r3, and r4 is activated. Tl, T2, T3, T4 are each A
AND of one of the ND-0R circuits 56, 5r, 58, and 59
input to the circuit. 50 is page information sent by the input/output channel device when accessing the storage device.

Reference numeral 50 does not encode page information, and one bit is assigned to each page, and information lines 51, 52, 53, and 54 corresponding to each page are connected to the AND-0R circuit 5.
It is input to the other AND circuit of 6, 51, 58, and 59.

The page information 50 is created by newly providing a specified area in one field of the channel command word CCW.
It can be set to any value using software. The gates of the N1OR circuits 56, 5r, 58, and 59 are controlled by a control signal 55 that controls the main memory access of the input/output channel device and a control signal R5 that controls the main memory access of the central control unit, respectively. The configuration is such that request signal lines 31, 32, 33, and 34 are energized. FIG. 3 is a block diagram showing in detail the page access response signal reception control circuit 40 in FIG. 1. Holding flip-flops 81, 82, 83, 84 are set when page access requests 31, 32, 33, 34 are activated, respectively, and page access response signals 41, 42, 4 are set.
3, 44 are configured to be returned and set. 46, 4r, 48, which also shows page implementation information.
49, the corresponding flip-flop is reset even if the corresponding page is not mounted. The inverted outputs of holding flip-flops 81, 82, 83, and 84 are input to AND circuit 90, which energizes flip-flop 91 when all of them are in the reset state. 91, 92, and 93 are differentiating circuits that differentiate the output of 90, and send out a page access response reception completion signal.

When multiple pages are accessed simultaneously by using the configuration shown in Figure 3, the access response reception is completed when the slowest Acoupis response among all accessed pages is received, so the response time for each page is Even if they are different, the control sequence of the central controller will not be disturbed. Furthermore, in order to prevent the access response receiving circuit from becoming stuck due to the access response signal not being returned due to unimplemented pages, a means for detecting unimplemented pages is provided to improve the expandability of the main memory. There is. In this way, by introducing the multiple page simultaneous writing method according to the present invention,
Program modules and data can be overlaid on program and data pages with a single I/O instruction.

In addition, since many conventional secondary storage devices employ rotating bodies such as magnetic drums, there is a waiting period of several milliseconds or more on average for a data transfer command, but according to the present invention, there is a waiting period of several milliseconds or more on average. The overlay processing speed can be increased by several milliseconds or more, and the processing capacity of the entire system can be improved. moreover,
According to the present invention, it is possible to speed up overlay processing in small and medium-sized exchange systems, etc. by providing a configuration in which simultaneous writing is possible to any plurality of pages having mutually different speeds.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of the page access control circuit shown in FIG. 1, and FIG. 3 is a block diagram of the page access response receiving circuit shown in FIG. It is a detailed block diagram. 10...Main storage device, 20...Storage device control unit, 30...Page access control circuit,
40...Page access response receiving circuit, 21.
...Data bus, 31, 32, 33, 34...
...Page access request signal, 41, 42, 43, 4
4...Response signal, 46, 4r, 48, 49...
...Page implementation display line, 50...Page information from input/output channel device, 61...Page register when fetching central control unit command, 62...
・Page register at the time of central control unit operand fetch, 65...Page switching circuit, RO...
・Decoder, 56, 5r, 58, 59...AN
D-0R circuit, 81, 82, 83, 84... Page access response reception control flip-flop, 91, 9
2,93... Differential circuit.

Claims (1)

[Claims] 1. In a data processing system having a main memory device composed of a plurality of pages and a storage device control unit that controls the main memory device, the access time of each page of the main memory device composed of the plurality of pages is different speeds. Yes, the storage device control unit includes means for receiving access response signals from each page of the main storage device, means for detecting an uninstalled page in the main storage device, and a means for detecting an access to an uninstalled page. means for bringing the access response reception means for the page into an access response reception state within a predetermined time, and when multiple pages are accessed simultaneously, an access response reception completion signal is sent when all the access response signals from the accessed multiple pages are received. 1. A storage device control method, comprising: means for generating.