JPS5730165A - Random access memory - Google Patents

Random access memory

Info

Publication number
JPS5730165A
JPS5730165A JP10397780A JP10397780A JPS5730165A JP S5730165 A JPS5730165 A JP S5730165A JP 10397780 A JP10397780 A JP 10397780A JP 10397780 A JP10397780 A JP 10397780A JP S5730165 A JPS5730165 A JP S5730165A
Authority
JP
Japan
Prior art keywords
memory cell
cel1
write
writing
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10397780A
Other languages
Japanese (ja)
Other versions
JPS6232555B2 (en
Inventor
Hirohisa Karibe
Osamu Uechi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10397780A priority Critical patent/JPS5730165A/en
Publication of JPS5730165A publication Critical patent/JPS5730165A/en
Publication of JPS6232555B2 publication Critical patent/JPS6232555B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

PURPOSE:To simplify an information processing sequence by writing constant information in addresses having correspondence specially regarding a RAM. CONSTITUTION:For the writing operation of a memory cell CEL1, an address ADR changes from a 1 to a 0 and is selected and a memory cell CEL2 is initialized. Since the memory cell CEL is selected for actual use, a read/write switching control line R/W has a write signal of a 1, and when a data bus DTB has a signal in the application of a write-clock-pulse application line WCLK, the writing of the memory cell CEL1 is done. An output terminal OPT is detected when the actually used CEL1 among memory cells has a 1.
JP10397780A 1980-07-29 1980-07-29 Random access memory Granted JPS5730165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10397780A JPS5730165A (en) 1980-07-29 1980-07-29 Random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10397780A JPS5730165A (en) 1980-07-29 1980-07-29 Random access memory

Publications (2)

Publication Number Publication Date
JPS5730165A true JPS5730165A (en) 1982-02-18
JPS6232555B2 JPS6232555B2 (en) 1987-07-15

Family

ID=14368377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10397780A Granted JPS5730165A (en) 1980-07-29 1980-07-29 Random access memory

Country Status (1)

Country Link
JP (1) JPS5730165A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01233636A (en) * 1988-03-08 1989-09-19 Internatl Business Mach Corp <Ibm> Memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525176A (en) * 1978-08-14 1980-02-22 Nec Corp Memory unit control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525176A (en) * 1978-08-14 1980-02-22 Nec Corp Memory unit control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01233636A (en) * 1988-03-08 1989-09-19 Internatl Business Mach Corp <Ibm> Memory
JPH0516062B2 (en) * 1988-03-08 1993-03-03 Intaanashonaru Bijinesu Mashiinzu Corp

Also Published As

Publication number Publication date
JPS6232555B2 (en) 1987-07-15

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