JPS57169842A - Data receiver - Google Patents

Data receiver

Info

Publication number
JPS57169842A
JPS57169842A JP56054403A JP5440381A JPS57169842A JP S57169842 A JPS57169842 A JP S57169842A JP 56054403 A JP56054403 A JP 56054403A JP 5440381 A JP5440381 A JP 5440381A JP S57169842 A JPS57169842 A JP S57169842A
Authority
JP
Japan
Prior art keywords
signal
address
counter
data
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56054403A
Other languages
Japanese (ja)
Inventor
Yoshiki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP56054403A priority Critical patent/JPS57169842A/en
Publication of JPS57169842A publication Critical patent/JPS57169842A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To realize the optional reading by an address designation given from a microprocessor, by using a counter that counts the synchronizing signals plus plural RAMs which store the synchronising signals with every bit and replacing the addresses successively with every unit data. CONSTITUTION:When the write control signal WR is applied to a terminal T3 from the muCPU side, a counter 1 works by the rise of the synchronizing signal SY. Then an AND gate 41 opens to designate an address A1 of storage elements 21-2n, and the data input signal DA is stored in a storage element 2 by the fall of the signal SY. The address of the element 2 is replaced by the counter 1 while the signal WR is applied to perform the writing of data successively. The control signal RE read out to a terminal T4 from the muCPU is applied to the address signal AD via terminals T51-T5n. Thus the contents of a memory 2 is read through a data output terminal DOU, AND gates 61-6n and terminals T61-T6n respectively.
JP56054403A 1981-04-13 1981-04-13 Data receiver Pending JPS57169842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56054403A JPS57169842A (en) 1981-04-13 1981-04-13 Data receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56054403A JPS57169842A (en) 1981-04-13 1981-04-13 Data receiver

Publications (1)

Publication Number Publication Date
JPS57169842A true JPS57169842A (en) 1982-10-19

Family

ID=12969721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56054403A Pending JPS57169842A (en) 1981-04-13 1981-04-13 Data receiver

Country Status (1)

Country Link
JP (1) JPS57169842A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62299153A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Serial data source and sink
JPS62299143A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Serial data source and sink
JPS6367054A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Transmitter for serial data
JPS6367053A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Receiver for serial data
JPS6367052A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Transmitter for serial data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54145444A (en) * 1978-05-08 1979-11-13 Toshiba Corp Control system of buffer memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54145444A (en) * 1978-05-08 1979-11-13 Toshiba Corp Control system of buffer memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62299153A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Serial data source and sink
JPS62299143A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Serial data source and sink
JPS6367054A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Transmitter for serial data
JPS6367053A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Receiver for serial data
JPS6367052A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Transmitter for serial data

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