GB1438861A - Memory circuits - Google Patents

Memory circuits

Info

Publication number
GB1438861A
GB1438861A GB2336073A GB2336073A GB1438861A GB 1438861 A GB1438861 A GB 1438861A GB 2336073 A GB2336073 A GB 2336073A GB 2336073 A GB2336073 A GB 2336073A GB 1438861 A GB1438861 A GB 1438861A
Authority
GB
United Kingdom
Prior art keywords
matrix
write
bit
address
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2336073A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of GB1438861A publication Critical patent/GB1438861A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

1438861 Matrix stores NIPPON ELECTRIC CO Ltd 16 May 1973 [16 May 1972] 23360/73 Heading G4C A memory circuit employing a plurality of IGFETs comprises a plurality of operating circuits, one of which is a matrix of memory cells, and an arrangement for controlling the commencement of operation of each of the plurality of operating circuits, which operate in a predetermined sequence to cause address signals to be applied to the matrix and to effect reading of a bit stored in the matrix or to write a bit therein. A control circuit 31, Fig. 3, within the control arrangement has an operating time equal to that of an operating circuit 3 and is arranged to receive the same input signal as circuit 3 for initiating operation of a subsequent operating circuit. The storage cells 6 are arranged as a matrix of 32 32-bit words. Refreshing.-At time # 0 the address signals x 0 . . . x 9 are generated in true and complement form. At time 91 the address signals are applied to two groups 3, 3<SP>1</SP>, each of 32 decoders, to select one decoder in each group. At # 2 the output from one (3) of the selected decoders causes read-out of the corresponding group of 32 cells 6 to read-digit lines RDL. At # 3 transmission circuits 9 are enabled to pass the word from the read-digit lines RDL to the write-digit lines WDL. At # 4 the output from the same (3) selected decoder selects the write address lines WAL to cause the word to be rewritten in the selected address. Writing.-At # 5 one of the write digit lines, selected by the output of the other decoder (3<SP>1</SP>), is connected to terminal IN so that an input bit is impressed on the corresponding cell at the selected address. Reading.-At # 5 the bit on the selected write digit line passes to terminal OUT.
GB2336073A 1972-05-16 1973-05-16 Memory circuits Expired GB1438861A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4887672A JPS5240937B2 (en) 1972-05-16 1972-05-16

Publications (1)

Publication Number Publication Date
GB1438861A true GB1438861A (en) 1976-06-09

Family

ID=12815473

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2336073A Expired GB1438861A (en) 1972-05-16 1973-05-16 Memory circuits

Country Status (5)

Country Link
JP (1) JPS5240937B2 (en)
DE (1) DE2324769C3 (en)
FR (1) FR2184865B1 (en)
GB (1) GB1438861A (en)
IT (1) IT987474B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2360113A (en) * 2000-03-08 2001-09-12 Seiko Epson Corp Dynamic random access memory

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011632A (en) * 1973-06-01 1975-02-06
US3964030A (en) * 1973-12-10 1976-06-15 Bell Telephone Laboratories, Incorporated Semiconductor memory array
US3969706A (en) 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
JPS51142925A (en) 1975-06-04 1976-12-08 Hitachi Ltd Address buffer circuit
JPS51163830U (en) * 1975-06-20 1976-12-27
JPS5284929A (en) * 1976-01-07 1977-07-14 Hitachi Ltd Memory system
JPS52106640A (en) * 1976-03-05 1977-09-07 Hitachi Ltd Memory peripheral circuit
US4042915A (en) * 1976-04-15 1977-08-16 National Semiconductor Corporation MOS dynamic random access memory having an improved address decoder circuit
JPS5810799B2 (en) 1976-06-01 1983-02-28 テキサス インスツルメンツ インコ−ポレイテツド semiconductor storage device
DE2760461C2 (en) * 1976-06-01 1994-04-21 Texas Instruments Inc Semiconductor memory unit with matrix array
JPS5325323A (en) * 1976-08-23 1978-03-09 Hitachi Ltd Pre-sense amplifier
JPS5360125A (en) * 1976-11-11 1978-05-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory unit
JPS5453652A (en) * 1977-10-07 1979-04-27 Denyo Co Ltd Battery welder
JPH0124644Y2 (en) * 1979-08-28 1989-07-26
US4539661A (en) * 1982-06-30 1985-09-03 Fujitsu Limited Static-type semiconductor memory device
JPS5956292A (en) * 1982-09-24 1984-03-31 Hitachi Ltd Semiconductor storage device
JPS6075510A (en) * 1983-09-30 1985-04-27 Mitsubishi Heavy Ind Ltd Method for supplying coolant scrap in continuous steel making furnace
JPS60242593A (en) * 1984-05-16 1985-12-02 Hitachi Micro Comput Eng Ltd Semiconductor storage device
JPH0736273B2 (en) * 1984-11-26 1995-04-19 株式会社日立製作所 Semiconductor integrated circuit
DE3745016C2 (en) * 1986-11-11 1996-01-18 Mitsubishi Electric Corp Dynamic semiconductor memory with memory cell field
JP2511910B2 (en) * 1986-11-11 1996-07-03 三菱電機株式会社 Semiconductor memory device
JPS63275093A (en) * 1987-05-06 1988-11-11 Nec Corp Semiconductor storage device
US4926387A (en) * 1988-12-27 1990-05-15 Intel Corporation Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells
KR100296964B1 (en) * 1999-06-28 2001-11-01 박종섭 packet command driving type memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1100461A (en) * 1963-10-02 1968-01-24 Automatic Telephone & Elect Improvements in or relating to magnetic core matrix data storage devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2360113A (en) * 2000-03-08 2001-09-12 Seiko Epson Corp Dynamic random access memory
GB2360113B (en) * 2000-03-08 2004-11-10 Seiko Epson Corp Dynamic random access memory

Also Published As

Publication number Publication date
FR2184865A1 (en) 1973-12-28
IT987474B (en) 1975-02-20
DE2324769B2 (en) 1978-12-21
DE2324769A1 (en) 1973-12-06
FR2184865B1 (en) 1980-03-07
JPS5240937B2 (en) 1977-10-15
DE2324769C3 (en) 1987-07-09
JPS4914052A (en) 1974-02-07

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19930515