JPH0736273B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit technology and a technology effective when applied to a semiconductor integrated circuit equipped with a rewritable read-only semiconductor memory device, for example, EPROM ( The present invention relates to a technology effectively applied to a single-chip microcomputer including an electrically programmable read-only memory).

[Background Art] A data processing LSI such as a single-chip microcomputer (hereinafter referred to as a single-chip microcomputer)
Some (large-scale integrated circuits) have a read-only storage device called a ROM (read-only memory, hereinafter also referred to as ROM) for storing system operation programs and the like integrally. Conventionally, the built-in ROM in a single-chip microcomputer is generally composed of a mask ROM that cannot be rewritten, but a rewritable memory called EPROM (EPROM) may be mounted on the package.

For the single-chip microcomputer in which the mask ROM is built in the chip, refer to the semiconductor data book “8 / 16-bit microcomputer”, pages 45 to 82, published by Hitachi, Ltd. in September 1982. For EPROM-installed single-chip microcomputers, see Data Book No. 35.
It is explained in greater detail on pages 0-389.

By the way, in the above-mentioned single-chip microcomputer equipped with ROM (including those on-chip), the sense amplifier (read circuit) is operated continuously during the ROM read cycle. However, the ROM mounted on the single-chip microcomputer does not need to continuously operate the sense amplifier during the read cycle, and after the output of the read data is confirmed, the latch does not need to operate the sense amplifier. . Therefore, it has been clarified by the present inventor that the conventional single-chip microcomputer has a disadvantage that power consumption in the sense amplifier is large.

Incidentally, in a conventional semiconductor memory such as a static RAM, there has been proposed a semiconductor memory in which the operation of the sense amplifier is stopped after the output of the read data is fixed in order to reduce the power consumption. However, in a memory such as a static RAM that is not an on-chip type, it is operated by a control signal such as a chip enable signal supplied from a microcomputer or the like, and a timing pulse (clock) is externally applied. It is not possible. Therefore, in order to dynamically operate the sense amplifier to reduce power consumption, a timing generation circuit such as an address change detection circuit that detects a change in an address signal supplied from the outside and forms a timing signal must be provided inside. The larger the number of address inputs, the larger and complicated the circuit becomes.

[Object of the Invention] An object of the present invention is to reduce power consumption in an LSI having a ROM mounted therein without providing a complicated circuit such as an address change detection circuit.

Another object of the present invention is to provide an LSI in which a ROM is mounted,
An object of the present invention is to provide a technique capable of accurately detecting the stop timing of the sense amplifier.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, a semiconductor integrated circuit including a CPU, a memory having a memory array and a peripheral circuit, and a control circuit for controlling the operation of the peripheral circuit, the high level periods of which do not overlap with each other in the CPU. As described above, the first and second internal clock signals which are out of phase with each other by a half cycle, and the external synchronizing signal which has a frequency of 1/2 of these internal clock signals and has substantially the same phase as the first clock signal are formed. The semiconductor integrated circuit further includes a dummy memory array having dummy data lines and a read circuit of the dummy memory array, and the peripheral circuit is connected to the data lines of the memory array. And a latch circuit that receives the output of the sense amplifier circuit. Only in Le period the first
Means for forming a first signal for initializing the data line and the dummy data line to a low level in the same manner in synchronization with the clock signal, and a low level in synchronization with the fall of the first signal. Means for forming a second signal for precharging the data line and the dummy data line, and a high level signal in synchronization with the fall of the second signal, the sense amplifier circuit and the dummy Means for forming a third signal for initiating precharge of the read circuit of the memory array, the read circuit monitoring the dummy read data and performing a read operation when the data is confirmed. The control circuit outputs a signal to stop, and the control circuit outputs the read data after the read data is latched in the latch circuit based on the output signal of the read circuit. A semiconductor integrated circuit formed by outputs a control signal to the Nsuanpu circuit inoperative.

As a result, the data line and the dummy data line are initialized to the low level for each access operation of the built-in ROM, and then the data line and the dummy data line are precharged, so that the EPROM write level is not affected. , Read accurate data early,
The address dependency of the memory array can be prevented.

The present invention will be specifically described below with reference to the drawings.

[Embodiment] FIG. 3 shows an example of the configuration of a single-chip microcomputer to which the present invention is applied. Each circuit portion shown in the same figure is formed on one semiconductor substrate such as silicon. To be done.

The single-chip microcomputer of this embodiment is not particularly limited, but includes a microprocessor (hereinafter referred to as CPU) 1 for controlling an internal execution unit and the like according to a program,
A program that stores the operating programs of this CPU1
ROM 2, RAM (Random Access Memory) 3 which mainly provides a work area for CPU 1, serial communication interface circuit 4, timer circuit 5 and four input / output ports 6a to 6d. Are connected to each other via an internal address bus 7a and an internal data bus 7b.

Although not shown in detail, the CPU 1 has a program counter that holds the address of an instruction or data to be read next, an instruction register from which the instructions of the program are fetched in order,
Execution of a control unit that consists of a micro ROM that stores micro programs or a random logic circuit that forms a control signal according to the instruction fetched in the instruction register, and various registers such as an accumulator and ALU (arithmetic logic unit) It is composed of a unit and.

Of the input / output ports 6a to 6d, the address bus 7a and the data bus 7b are connected to the port 6d, and the address bus 7a and the data bus 7b are connectable to the port 6c via the multiplexer 8. Further, there is provided a mode switching circuit 9 which determines an operation mode after resetting the microcomputer by setting an appropriate external terminal to a predetermined state.
The input / output port 6d is operated by the mode setting circuit 9 so as to have the data input / output function or the address output function, and the port 6c is similarly operated by the mode switching circuit 9
It is operated to have a data input / output function or a function to multiplex the data bus and the address bus under the control of.

As a result, the address space of the single-chip microcomputer of this embodiment can be expanded.

And in this embodiment, the program ROM 2 is
Although not particularly limited, it is composed of a rewritable EPROM having a storage capacity of, for example, 4k × 8 bits.

In addition, the single-chip microcomputer has an address decoder 10 for selectively operating the program ROM 2 inside.
When the address data output from the CPU 1 on the address bus 7a is within the address range given to the program ROM (EPROM) 2, it is enabled by the address decoder 10 by decoding it. The signal φ _E is output so that the program ROM 2 is activated.

Whether the mode switching circuit 9 is in a mode in which it operates as a normal microcomputer (hereinafter referred to as a microcomputer mode) depending on the input state of a dedicated mode setting external terminal 11 (hereinafter referred to as a microcomputer mode) or a data writing mode to the program ROM 2 (Hereinafter referred to as "EPROM mode"), and the operation mode inside the microcomputer is determined accordingly. When the mode switching circuit 9 sets the inside to the EPROM mode, the circuits other than the program ROM 2 and the input / output ports required for data input (CPU1, RAM3, etc.) are disconnected from the internal address bus 7a and the data bus 7b. . This makes only the EPROM visible to the outside of the chip. In this EPROM mode, the internal clock signals φ ₁ and φ ₂ are not formed either, and the program ROM (EPRO
M) 2 is statically operated.

Although not shown, the CPU1 in FIG. 3 divides the original oscillation signal such as 4 MHz supplied from the outside so that the high-level periods do not overlap with each other as shown in FIG. And two internal clock signals φ ₁ and φ ₂ that are out of phase with each other, and these internal clock signals φ
There is provided a clock pulse generator which forms an external periodic signal E having a frequency of 1/2 of ₁ and φ ₂ and having almost the same phase as the clock φ ₁ . Then, the internal clock signals φ ₁ and φ ₂ are supplied to each circuit block in the chip such as a control circuit (described later) in the program ROM 2 and operate those circuits in synchronization with the CPU 1.

The external synchronization signal E is output to the outside of the single chip microcomputer and supplied to the peripheral device as a system clock.

FIG. 4 shows an embodiment of the program ROM 2 composed of EPROM, and FIG. 5 shows its timing chart.

The program ROM 2 of this embodiment is not particularly limited, but the memory array is divided into eight memory blocks 20a to 20h, and each memory block is arranged in a matrix of 256 × 16 FAMOS (floating gate type). A non-volatile memory cell MC composed of a MOS transistor).

Further, a dummy memory array 21 in which 256 memory cells are arranged in a line along the data line is provided along with the memory blocks 20a to 20h.

256 word lines W ₁ to _W-256 of the memory block 20a~20h and the dummy memory array 21 are formed respectively in succession, to decode takes in address signals A ₀ to A ₇ on the address bus 7a X One of them is set to the selection level by the decoder 22. FAMOS configuring memory cell MC
Is written in advance, that is, when charge is injected into the floating gate electrode, the threshold voltage is set to the selected level of the word lines W _{1 to} W ₆₄ (about 5
V) a little higher. Further, the threshold voltage of the so-called erased FAMOS in which programming is not performed is made lower than the selection level of the word line.

Therefore, in each row in which the control gate electrode is connected to the word line set to the selection level by the X decoder 22,
The FAMOS (memory cell MC) is brought into a non-conducting state or a conducting state, respectively, depending on the writing or erasing state.

16 data lines DL ₁ through DL ₁₆ to the drain terminal of each row are connected in the memory block 20a, respectively MOSFET
(Insulated gate type field effect transistor), and is connected to the common data line CDL ₁ through column switches Qc _{1 to} Qc ₁₆ of which one is turned on by the Y decoder 23. Other memory blocks 20b-20h
Each of the data lines therein is also connected to the common data lines CDL _{2 to} CDL ₈ by the column switch circuits 24b to 24h.

The Y decoder 23 receives the address signals A ₈ -from the address bus 7a.
By taking in A ₁₁ and decoding it, a selection signal of the data line is formed and applied to the gate terminals of the column switches Qs _{1 to} Qs ₁₆ to turn on one of them.

The common data lines CDL _{1 to} CDL ₈ provided for the memory blocks 20a to 20h are depletion type MOSFETs, respectively.
It is connected to a read circuit 25a~25h via the control transistor Qw ₁ ~Qw ₈ made of.

Although not particularly limited, the dummy data line DLd in the dummy memory array 21 is connected to the dummy read circuit 26 via the dummy column switch Qcd and the dummy write control MOSFET Qwd which are always on. At the time of data reading, the common data lines CDL _{1 to} CDL are supplied by the write control signal ▲ ▼ based on the mode designation signal EPM output from the mode switching circuit 9 and the control signal input from the outside.
Write control MOSFETQw ₁ ~Qw ₈ connected to L ₈ are in a conductive state, a read signal D ₀ to D ₇ level of the data line by the read circuit 25a~25h is amplified respectively is formed, on the data bus 7b Is output to.

At this time, as will be described in detail later, by detecting the level of the dummy data line DLd by the dummy read circuit 26, the read end timing is known, and the control signal ▲ ▼ or LTC output from the control circuit 27 described later is output. Etc. are changed to control the read circuits 25a to 25h and 26 (see FIG. 5).

On the other hand, the source terminal of the FAMOS constituting each memory cell in each memory block 20a~20h is connected to a common source line Cs ₁ to CS ₁₆ for each column, these common source lines Cs ₁ ~
Cs ₁₆ is a pair of enhancement type MOSFETs Q _{N1 to} Q _N8 and depletion type MOSFET Q _D1 connected in parallel for each column.
~ Connected to ground through Q _D8 . The pair of MOSFETs Q _{N1 to} Q _N8 and Q _{D1 to} Q _D8 are controlled by the write control signal ▲ ▼.

That is, at the time of data reading, the high level write control signal ▲ ▼ is applied to the gate terminal,
Both MOSFETs Q _N1 and Q _D1 are turned on and common source lines Cs _{1 to} Cs ₈
To the ground point. In addition, when writing data, the low-level write control signal ▲ ▼ is applied to the gate terminal to turn on only the depletion type MOSFET Q _D1 and connect the common source line Cs through a resistor of appropriate size.
_{1 to} Cs ₈ are connected to the ground point.

As a result, at the time of writing, a current flows from the common source line toward the ground point, the potential of the common source line rises, and thereby a leak current is prevented from flowing to an unselected memory cell.

In the above case, the transistor connected between the common source lines Cs _{1 to} Cs ₈ and the ground point is the depletion type MOSFET Q _D1.
To Q _D8 may be only, but in this embodiment, this and by connecting the enhancement type MOSFET Q _N1 to Q _N8 in parallel, adapted to be lowered the resistance of the common source line at the time of reading.

By reducing the resistance value of the common source lines Cs _{1 to} Cs ₈ , the level difference of the data lines at the time of reading can be increased.

Although not particularly limited, in this embodiment, for the eight memory blocks 20a to 20h and the dummy memory array 21,
MOSFETs Q _{N1 to} Q _N8 and Q _{D1 to} Q _D8 are provided, respectively, and each common source line is connected to the ground point.

Further, write circuits 28a to 28h are connected to the common data lines CDL _{1 to} CDL ₈ provided for each of the memory blocks 20a to 20h, and the write circuits 28a to 28h write data to each memory cell. Writing is performed. Writing circuit
In 28a to 28h, a write voltage V _PP , such as 12.5 V, higher than the power supply voltage (5 V) applied in the microcomputer mode is applied to a predetermined pin (shared with the signal pin in the microcomputer mode), Further, when the mode switching circuit 9 shown in FIG. 3 determines that the mode is the EPROM mode based on the input state of the mode setting terminal 11, the write operation is performed based on the mode designation signal EPM output from the mode switching circuit 9. To do.

That is, in the EPROM mode, the write circuits 28a to 28h write data Di that is externally placed on the data bus 7b.
n ₀ through Din ₇ uptake by generating a voltage corresponding to the data, the common data line in the memory block 20a~20h CDL ₁ ~CDL ₈
Apply to. Applied write voltage to the common data line CDL ₁ ~CDL ₈ is supplied to the data line DL through a column switch Qc selectively are turned on by the time the Y decoder 23.

Further, in the EPROM mode, the X decoder 22 supplies a selection signal of a level such as 12.5V, which is higher than the selection level (5V) in the microcomputer mode, to one of the word lines.

When writing to the selected memory cell, the X decoder 22 is applied to the control gate electrode of the memory cell.
Applies a high select signal such as 12.5V, and the write circuits 28a to 28h supply a high write voltage such as 12.5V to the data line DL having its drain terminal connected through the column switch Qc. by this,
Charge is injected into the floating gate of the selected memory cell to put it in the written state.

In this case, the common data lines CDL ₁ ~CDL connected control transistor to ₈ Qw _{1 ~Qw 8} is a low level of write based on the control signal inputted from the mode designating signal EPM and external output from the mode switching circuit 9 Since the control signal ▲ ▼ is applied, when the potential on the read circuit side becomes approximately 3 V or more, the cutoff state is set. Therefore, the write circuit 28
The high write voltage supplied to the common data lines CDL _{1 to} CDL _{16 from a} to 28h is not transmitted to the read circuits 25a to 25h.

In the above case, the dummy memory cells forming the dummy memory array 21 always read the data corresponding to the erased state as will be described later, so it is not necessary to write the data to the dummy memory cells.

Next, the timing of the input / output signals of the control circuit 27 will be described with reference to FIG.

The control signal ▲ ▼ is changed to the low level in synchronization with the clock φi formed in the control circuit based on the system clock E and the internal clock signal φ ₁ .
The clock φi is a signal which changes in the same manner in synchronization with the clock φ ₁ only during the low level period of the system clock E, and the control circuit 27 sends this clock φi to the read circuits 25a to 25h and 26 to initialize it. Let

Then, the clock φ for this read circuit initialization
The operation of the read circuits 25a to 25h and 26 is started by the control signal {circle around (5)} which is changed to the high level in synchronization with the fall of i.

The control circuit 27 sets the precharge signal ▲ ▼ to a low level in synchronization with the fall of the control signal ▲ ▼ and supplies it to the read circuits 25a to 25h and 26 to start precharging of an internal sense amplifier (described later). . Then, the level detecting means provided in the control circuit 27 detects the level of the dummy data line DLd, and when the dummy data line DLd rises above a predetermined level, the precharge signal φp is raised. There is.

When the precharge is completed, the control circuit 27
Raises the drive signal φx of the X decoder 22 to drive the X decoder 22. As a result, the level of the selected one word line W rises, and after a certain time, the read data D _{0 to} D ₇ output from the read circuits 25a to 25h and the dummy read data output from the dummy read circuit 26. Dd
Changes.

The control circuit 27 monitors the dummy read data Dd, changes the control signal ▲ ▼ to a high level when the data is determined, and stops the operations of the read circuits 25a to 25h and 26.

Further, the control circuit 27 synchronizes with the read circuits 25a to 25h in synchronization with the rise of the drive signal φx of the X decoder 22.
The control signal LTC supplied to 26 is changed to high level.
Then, the latch circuits (described later) in the read circuits 25a to 25h and 26 start the latch operation and capture the output of the sense amplifier. Then, the control signal LTC is changed to the low level in synchronization with the operation of the read circuits 25a to 25h, 26 being stopped by the rise of the control signal ▲ ▼, whereby the latch circuit finishes latching the data and the data To the state of holding. While the latch circuit holds the data, the data of the read circuits 25a to 25h are output onto the data bus 7b.

Next, FIG. 1 shows an example of a specific circuit configuration of one of the read circuits 25a to 25h and a part of a memory array connected to it.

Unless otherwise specified below, each MOSF that constitutes a circuit is
It is assumed that the ET has an N-channel shape.

For facilitating the understanding, one FAMOS Qf and one of a plurality of column switches forming a memory cell in the memory array are typically shown in this figure.
The node n ₁ to which the source terminal of is connected to the common source line CS in FIG. 4 and the node to which the drain terminal is connected
n ₂ corresponds to the data line DL. The column switch Qc is connected to the node n ₂ corresponding to the data line DL. The write control transistor is shown by Qw. Therefore, the connection node n ₃ between the column switch Qc and the transistor Qw
Corresponds to the common data line CDL.

The gate terminal of the FAMOS Qf is connected to the X decoder 22 of FIG.
The selection signal X output from the column switch Qc is applied via the word lines (W _{1 to} W ₂₅₆ ), and Y is applied to the gate terminal of the column switch Qc.
The selection signal Y output from the decoder 23 is applied. A control signal ▲ ▼ is applied to the gate terminal of the write control transistor Qw.

The read circuit 25a includes a sense amplifier SA, a latch circuit 34, and an output circuit OC. The output circuit OC is a latch circuit 34
And a data bus and a tri-state circuit.

The sense amplifier SA is not particularly limited, but as shown in the figure, P-channel MOSFETs Q ₁ , Q ₃ , Q ₅ , Q ₈ and N-channel MOS
It is composed of FETs Q ₂ , Q ₄ , Q ₆ and Q _7, and a CMOS inverter 33.

The MOSFET Q ₁ is switch-controlled by the control signal ▲ ▼ and operates as a constant current source. MOSFET Q ₂ has signal φ
It is switch-controlled by i and is provided to discharge the node n ₄ .

The MOSFETs Q ₃ to Q ₇ constitute one differential amplifier circuit as a whole. That is, P-channel MOSFETs Q ₃ and Q ₅
Constitutes a current mirror load of N channel input differential amplification MOSFETs Q ₄ and Q ₆ , and N channel MOSFET Q ₇ constitutes an operating current source.

MOSFET Q ₄ has its gate coupled to node n ₄
Q ₆ has its gate coupled to a reference voltage source not shown. The reference voltage source is composed of, for example, a resistor voltage dividing circuit, although not particularly limited, and outputs a reference voltage Vref of an appropriate level to be supplied to the differential amplifier circuit by receiving the power supply voltage V _CC .

P-channel MOSFET Q ₈ is a precharge MOSFET.

The operation of the read circuit 25a having this configuration is as follows.

First, when the clock φi is set to the high level as shown in FIG. 5D, the MOSFET Q ₂ is turned on accordingly. Node n ₄ is initialized by MOSFET Q _{2 to} a level of approximately 0 volts.

Next, when the clock φi falls to the low level, the control signal ▲ ▼ and the precharge signal ▲ are synchronized with it.
▼ is lowered to the low level as shown in FIGS. 5E and 5F, respectively. Control signal, but not limited to
SAC is set to high level in synchronization with the control signal ▲ ▼ being set to low level.

The MOSFET Q ₇ is made conductive by setting the control signal SAC to a high level. In response to this, an operating current starts to flow in the differential amplifier circuit. In this case, the output node
The potential of n ₅ is set to the precharge level (high level) because the MOSFET Q ₈ is turned on by the low level precharge signal ▲ ▼. Signal ▲
When ▼ and SAC are set at the above timing, an operating current flows through the differential amplifier circuit regardless of the output node n ₅ of the differential amplifier circuit being set to the precharge level. The generation of the operating current in such a precharge period delays the timing when the control signal SAC is set to the high level substantially the same timing as the timing when the precharge signal ▲ ▼ is set to the high level again or more. It can be made substantially zero by delaying to the specified timing. However, in this case, the control signal
It should be noted that the circuitry (not shown) forming the SAC is somewhat complicated.

The MOSFET Q _{2 in} FIG. 1 is turned off by setting the timing signal φi to the low level as shown in FIG.

The precharge MOSFET Q ₁ has the fifth control signal ▲ ▼
As shown in FIG. E, it is made conductive by being brought to a low level. This causes node n ₄ to
Starts charging via ETQ ₁ .

Here, the address signals A ₀ to A ₁₁ supplied to the address bus 7a in FIG. 4 have respective levels synchronized with it when the system clock E is set to a low level as shown in FIG. 5A. Will be confirmed. In response to this, the level of the output of the Y decoder 23 is determined before the signal () is set to the low level. That is, one column switches corresponding to the address signal A ₈ to A ₁₁ is set in the on state.

Therefore, the selected data line DL (node n ₁ ) is connected to the control signal ▲
When ▼ is set to the low level, precharge starts via the control MOSFET Qw and the column switch Qc.

The read circuit 26 of FIG. 4 corresponds to the read circuit 25a of FIG.
And has substantially the same configuration as. By this, the fourth
The data line (hereinafter referred to as a dummy data line) DLd in the dummy memory array in the figure starts to be charged at the same timing as the data line to be selected in the memory array. Although not particularly limited, the MOSFETs Qcd and Qwd provided between the dummy data line DLd and the read circuit 26 have impedances substantially equal to the impedances of the column switch Qc and the control MOSFET Qw.

Therefore, the precharged state of the data line to be selected in the memory array can be simulated by the dummy data line DLd.

The level of the dummy data line DLd is monitored by the control circuit 27 shown in FIG.

When the precharge level of the dummy data line DLd reaches a predetermined level as shown in FIG. 5G, the precharge signal ▲ output from the control circuit 27 in response thereto.
▼ is returned to the high level as shown in FIG. 5F, and the drive signal φx is changed from the low level to the high level as shown in FIG. 5H.

The precharge MOSFET Q ₈ coupled to the output node n ₅ of the differential amplifier circuit is turned off by setting the signal ▲ ▼ to a high level.

The X decoder 22 in FIG. 4 is put into operation by setting the drive signal φx to the high level. In response to this, one of the plurality of word lines W ₁ to W ₂₅₆ corresponding to the address signals A ₀ to A ₇ is set to the selection level (high level) substantially equal to the power supply voltage V _CC .

Here, the FAMOS Qf as the memory cell has one of the high threshold voltage and the low threshold voltage according to the write data in advance.

If FAMOSQf has a high threshold voltage, its FAM
OSQf remains off even if the word line is set to the selection level. Therefore, in this case, no direct current path is formed between the circuit node n _{4 of} FIG. 1 and the ground of the circuit. The node n ₄ remains at the precharge level (high level). The data line DL (node n ₂ ) also remains at the precharge level.

Conversely, if FAMOS Qf has a low threshold voltage, that FAMOS Qf will be turned on accordingly when the word line is brought to the select level. Therefore, in this case, a direct current path formed by the control MOSFET Qw, the column switch Qc, the FAMOS Qf, and the MOSFETs Q _N1 and Q _D1 is formed between the circuit node n ₄ and the ground point of the circuit. Data line DL and node
n ₄ therefore begins to drop its respective level accordingly when the word line is selected.

According to this embodiment, the level of the dummy data line DLd is referred to in order to detect whether or not the levels of the node n ₄ and the data line DL have been changed from the precharge level to the readable level.

Each FAMOS transistor in the dummy memory array 21 is set in the unwritten state and has a low threshold voltage as described above.

Therefore, when one of the word lines is selected, the charge on the dummy data line DLd starts to be discharged through the FAMOS transistor, so that the potential thereof is lowered as shown in FIG. 5G. . The level of the dummy data line DLd is detected by the read circuit 26.

The output of the read circuit 26 is shown in FIG. 5J when the level of the dummy data line DLd is lowered below a predetermined level.
It is changed from low level to high level as shown in.

The control circuit 27 controls the control signals ▲ ▼ and SA by setting the output of the read circuit 26 to the high level.
C is changed to a high level and a low level as shown in FIG. 5E.

As a result, the precharge MOSFET Q ₁ is turned off and the differential amplifier circuit is turned off. The threshold voltage of the read circuit 26 may be set to a value slightly higher than that of the read circuit 25a in consideration of the operation delay of the control circuit 27.

The latch control signal LTC for controlling the operation of the latch circuit composed of the clocked inverter 34 of FIG. 1 is not particularly limited, but is based on the monitoring result of the dummy memory array as shown in FIG. 5L. To a high level,
Control signal ▲ ▼ and SAC are high level,
Set to low level before returning to low level. The clocked inverter 34 outputs the output signal of the level corresponding to the previous input signal regardless of the input signal when the latch control signal LTC is set to the high level, and the control signal LTC is set to the low level if the control signal LTC is set to the low level. Capture the input signal at that time. Therefore, the output of the clocked inverter 34 is changed as shown in FIG. 5K in response to changes in the control signal LTC.

FIG. 2 shows a circuit diagram of a sense amplifier which can be replaced with the sense amplifier SA of FIG.

In this embodiment, a constant current MOSFET Q ₁ for flowing a read current into each data line via a column switch Qc is provided between the drain terminal (node n ₄ ) of the control transistor Qw and the power supply voltage V _CC. , For current control to control that current
MOSFET Q ₈ is connected in series. Of these, MOSFET Q ₁
Is formed as a P channel type, and operates as a constant current source by applying a ground potential to its gate terminal.

The selected data line DL (node n ₃ ) is connected to the node n ₄ above.
And a feedback circuit 32 that controls the current flowing toward the data line by adjusting the gate voltage of the current control MOSFET Q ₈ according to the level of the data line DL. There is.

The feedback circuit 32 has a MOSF whose current is controlled by the potential of the data line DL by connecting the gate terminal to the node n _4.
ETQ ₉ and a control signal ▲ ▼ output from the control circuit 27 to the gate terminal P
It is composed of a channel type MOSFET Q ₁₀ .
Then, the potential of the connection node n ₅ between the MOSFETs Q ₉ and Q ₁₀ is applied to the gate terminal of the current controlling MOSFET Q ₈ .

The level detection circuit 31 includes a MOSFET Q ₁₁ having a source terminal connected to the node n ₄ and a P-channel load MOSFET Q ₁₂ connected between the drain terminal of the MOSFET Q ₁₁ and the power supply voltage V _CC . It is configured. MOSFET Q above
The potential of the node n ₅ in the feedback circuit 32 is applied to the gate terminal of ₁₁ and is turned on / off like the current control MOSFET Q ₈ connected to the data line. A node from which the read level of the data line is output to the gate terminal of MOSFET Q _12.
A potential of n ₄ is applied, and it acts as a variable resistance type load element.

The level detection circuit 31 and the feedback circuit 32 constitute a so-called sense amplifier. In this sense amplifier,
In addition to the MOSFETs Q _{9 to} Q _12, the discharging MOSFETs Q ₂ and Q ₁₃ are connected between the node n ₄ and the ground point and between the node n ₅ and the ground point, respectively.

An initializing clock φi supplied to the control circuit 27 is applied to the gate terminal of one of the discharging MOSFETs Q ₂ and, before the start of the operation of the sense amplifier (falling of the control signal ▲ ▼), the node n ₄ Pull out the charge. The control signal ▲ ▼ output from the control circuit 27 is applied to the gate terminal of the other discharging MOSFET Q ₁₃ , which is turned on before the sense amplifier is operated to extract the electric charge of the node n _5. , Set the sense amplifier to the stopped state. Control signal ▲
When ▼ is changed to low level and the sense amplifier starts to operate, the MOSFETs Q ₂ and Q ₁₃ are turned off and have no influence on the operation of the circuit.

The output node of the level detection circuit 31, that is, MOSFET Q ₁₁
And a connection node n ₆ between Q ₁₂ and
Are connected, and the output of the inverter 33 is input to the clocked inverter 34 as a latch circuit. And
The output of the clocked inverter 34 is amplified and inverted by the data output inverter 35 and output to the data bus 7b.

Although not particularly limited, each of the above inverters 33 to 35
Is a CMOS (complementary MOS) type. Further, the clocked inverter 34 is controlled by the control signal LTC from the control circuit 27 to perform a latch operation.

Further, the node n ₆ in the level detection circuit 31 and the power supply voltage
A MOSFET Q ₁₄ for output level correction and a MOSFET Qp for precharge are connected to V _CC . MOSFET Q ₁₄ and Qp
Are each formed as a P-channel type. The precharge signal φp output from the control circuit 27 is applied to the gate terminal of the precharge MOSFET Qp. When the control signal ▲ ▼ is changed from high level to low level and the sense amplifier starts operating,
First, the precharge signal φp pushes up the node n ₆ to the power supply voltage V _CC . As a result, the read data outputs D _{0 to} D ₇ are always set to the low level first.

Further, the output voltage Vco of the power supply voltage detection circuit 36 that detects the level of the power supply voltage V _CC and outputs a voltage corresponding to the level is applied to the gate terminal of the MOSFET Q ₁₄ for correcting the output level. As a result, the output of the sense amplifier, that is, the level detection circuit 31 is corrected according to the level of the power supply voltage Vcc. This will be described in detail later.

Next, the operation of the read circuit having the above configuration is as follows.

Control signal supplied from the control circuit 27 ▲ ▼
Changes from high level to low level, MOSFET Q ₁₀
Is turned on, MOSFET Q ₈ is turned off, and the operation of the sense amplifier is started. That is, the charge flows into the node n ₅ through the MOSFET Q ₁₀ which is turned on by the control signal ▲ ▼, and the level of the node n ₅ is raised. By this, MO
The SFETQ ₈ is turned on, and the current supplied from the constant current MOSFET Q ₁ flows into the node n ₄ . By this time, Y
The decoder 23 turns on one column switch Qc corresponding to the addresses A _{8 to} A ₁₁ . Therefore, the node
The current flowing into n ₄ flows into the data line DL through the selected column switch Qc and charges up the data line.

At this time, MOSFET Q _{11 is} also turned on, so that the precharge signal φp also precharges from the output node n ₆ side of the sense amplifier as described above. for that reason,
The data line DL is precharged promptly.

In addition, the precharging of the data line is also performed in the dummy memory array 21, and the control circuit 27 controls the data line DL in the dummy memory array 21.
The level of d is monitored, and when it exceeds a predetermined level, the precharge signal φp is raised to end the precharge. Further, in synchronization with the rise of the precharge signal φp, the drive signal φx output from the control circuit 27 is changed to the high level and the X decoder 22 is driven, whereby the level of the selected one word line rises. To be done.

Then, at the end of the precharge, the control signal LTC supplied to the clocked inverter 34 is changed to the high level, and the output of the sense amplifier starts to be taken. Then, the sense amplifier output at the time when the clocked inverter 34 starts the latch operation is initially set to the high level by the precharge, so the output of the output inverter 35 is initially the low level.

As described above, when the word line starts rising after precharging is completed, the threshold voltage differs depending on whether the FAMOS Qf of the memory cell selected by this is in the written state or the erased state. Data line DL (node
A difference occurs in the potential of n ₂ ). That is, the selected FAMO
When SQf is in the write state, the word line select level (about 5
Since FAMOSQf is turned off at V), the potential of the data line DL (node n ₂ ) is the same as that at the end of precharge. On the other hand, when the selected FAMOS Qf is in the erased state, the FAMOS Qf is turned on, so that the potential of the data line DL becomes low.

The potential of the data line DL, which has a difference as described above, passes through the column switch Qc and the write control transistor Qw to generate the node n ₄
MOSFET Q ₉ in the feedback circuit 32 is strongly turned on as the data line potential increases. Then, when the MOSFET Q ₉ is strongly turned on, the potential of the node n ₅ drops and the current control MOSF
ETQ ₈ will move in the direction of being shut off.

Therefore, when the selected FAMOS Qf is in the write state, M
OSFETQ ₈ is cut off, the current flowing toward the data line DL is limited, and the potential of the node n ₄ is in an equilibrium state at a high place. On the other hand, if the selected FAMOS Qf is in the erased state, the FAM
Since OSQf is conductive, the data line potential becomes low and the MOSFET
Q ₉ is weakly turned on and the potential at node n ₃ rises,
MOSFET Q ₈ keeps on. This allows constant current MO
The constant current supplied from SFETQ ₁ is MOSFET Q ₈ , Qw, Qc and
FAMOSQf and further flows to the ground point through MOSFETs Q _D1 and Q _N1 . As a result, an equilibrium state is reached where the potential of the node n ₄ is low because it is pulled to the side of FAMOS Qf with low impedance.

Therefore, the MOSFET Q ₁₁ that constitutes the level detection circuit 31 connected to the node n ₄ has the above-mentioned MOSFE depending on the potential of the node n _5.
Works exactly like TQ ₈ . Therefore, when the selected FAMOS Qf is in the write state, the MOSFET Q ₁₁ is cut off by the potential of the node n ₄ having a relatively high potential and the output node n ₄ is cut off.
The potential of ₆ maintains a high level. Also selected FAM
When OSQf is in the erased state, the potential of the output node n ₆ is pulled down by the potential of the node n ₄ and the output of the waveform shaping inverter 33 is inverted.

In this way, when the output of the sense amplifier is fixed,
Depending on the data line level, read data (inverter
35 output) dummy memory array designed to be inverted
The control circuit 27 that monitors the read data of 21 detects the inversion of the read data on the dummy side and detects the latch control signal.
Change LTC from high level to low level. As a result, the clocked inverter 34 stops latching the output of the sense amplifier (inverter 33) and holds the data latched immediately before.

Then, in synchronization with the fall of this latch control signal LTC, the control signal output from the control circuit 27
▼ is changed from low level to high level. Then, the MOSFET Q ₁₀ is cut off, current is not supplied to the feedback circuit 32, the MOSFET Q ₁₃ is turned on, the node n ₅ is fixed at a low level, and the MOSFET Q ₁₁ is turned off.
No current is passed through the level detection circuit 31, and the operation of the sense amplifier is stopped.

Thus, according to the above-described embodiment, the sense amplifier is a CMOS
Although it is composed of a circuit, the current flowing in the feedback circuit 32 and the level detection circuit 31 while the circuit is operating is limited only to the time when the sense amplifier is operated by the control signal ▲ ▼. Like However, the operation period of the sense amplifier, that is, the low level period of the control signal SAC is minimized by the control circuit 27, so that the power consumption of the sense amplifier is significantly reduced.

When the control signal ▲ ▼ is set to high level, the MOSF
Since ETQ _{8 is} also turned off, the current flowing toward the data line when the selected memory cell is in the write state is also cut, and the current consumption of the entire memory array at the time of reading is also reduced. Moreover, according to the above-described embodiment, the operation time of the sense amplifier becomes relatively short, especially when the cycle of the internal clock signals φ ₁ and φ ₂ becomes long, and the effect of reducing the power consumption becomes large. .

Next, a supplementary explanation will be given on the operation of the output level correcting MOSFET Q ₁₄ of the sense amplifier, which has been briefly described above.

As shown in the above embodiment, when the data line level is detected by the sense amplifier including the level detection circuit 31 and the feedback circuit 32, the memory cell causes a write failure and the threshold voltage of FAMOSQf becomes the word. If it is lower than the line selection level (V _CC ), as shown in FIG. 6, as the power supply voltage V _CC becomes higher, the sense amplifier output (node
turned down n potential of ₆₎ Vso, becomes lower than the logic threshold voltage V _TL of the next-stage inverter 33, there is a possibility that reading of erroneous data.

Therefore, in the above-described embodiment, the level of the power supply voltage V _CC is detected by the power supply voltage detection circuit 36, and the control voltage Vco having the characteristic shown in FIG. It is applied to the gate of use MOSFET Q _14. As a result, when the sense amplifier operates on the side where the power supply voltage V _CC is high, its output is corrected so as to increase in the tendency shown by the broken line A in FIG.

The voltage characteristic shown in FIG. 6 is an example, and varies depending on the characteristics and size of the elements (MOSFETs Q _{3 to} Q ₆ ) forming the sense amplifier. In short, it suffices to form the control voltage Vco that results in the output characteristics shown in FIG. 5 in relation to the characteristics of the sense amplifier.

Also, if the memory cell has a write error and the threshold value is not sufficiently high, the word line selection level at the time of reading is turned on a little and the data line level is hard to rise, so the read time becomes long. There is a risk that However, in the above embodiment, since the precharge MOSFET Qp is provided to precharge the word line in the non-selected state, it is possible to quickly raise the data line level by the precharge and perform good reading. There is.

In the above embodiments, the memory array is divided into eight blocks, the read circuits are provided corresponding to the respective blocks, and the 8-bit data is read in parallel. It goes without saying that the bit configuration of the memory array is not limited to that, and may be configured to 1 bit, 4 bits, 16 bits, or the like.

Further, the MOSFET Q ₁₄ for correcting the output level of the sense amplifier and the precharge MOSFET Qp in the above embodiment can be omitted.

Furthermore, the method of providing a dummy memory array to know the operation stop timing of the sense amplifier is not limited to the EPROM of a single-chip microcomputer, but can
It can also be applied to PROMs, etc.

[Effects] (1) Sense amplifier ROM rather than operating constantly
Since the sense amplifier is activated when the word line inside is selected and the level of the data line is determined by this, the output of the sense amplifier is latched and the sense amplifier is stopped after reading the data. The effect of shortening the operation period is that there is an effect that power consumption can be reduced without providing a complicated timing generation circuit such as an address change detection circuit.

(2) A dummy memory array and its sense amplifier are provided separately from the built-in ROM memory array, and the dummy memory array is pre-populated with data such that the data line level always changes by reading. Since the data of is read and detected, the operation of the sense amplifier is performed by the action that when the data read from the dummy memory array is fixed, the data read from the normal memory array is also fixed. It is possible to accurately detect the sense amplifier stop timing that minimizes the period.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, the configuration of the sense amplifier is not limited to that of the above-described embodiment, and various modifications can be considered. The present invention is effective when applied to a sense amplifier having a structure in which a through current flows during operation.

Further, in the above-described embodiment, the single-chip microcomputer in which the EPROM is formed on the chip has been described, but it goes without saying that the present invention is also applicable to the single-chip microcomputer in which the EPROM is mounted on the package.

[Field of Application] In the above description, the invention mainly made by the present inventor is described as being applied to a single-chip microcomputer having a built-in EPROM, which is the field of application which is the background of the invention, but the invention is not limited thereto. It can be used for an LSI with a built-in EPROM having an internal clock or an LSI with a built-in ROM, and also for semiconductor memory devices in general.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a read circuit used in an LSI incorporating an EPROM according to the present invention, FIG. 2 is a circuit diagram of another embodiment, and FIG. FIG. 4 is a block diagram showing an example of a configuration of a single-chip microcomputer with a built-in EPROM, FIG. 4 is a circuit configuration diagram showing an embodiment of an on-chip EPROM circuit, and FIG. 5 shows the operation of the EPROM circuit. FIG. 6 is a timing chart showing the power supply voltage dependency of the sense amplifier output of the above embodiment, and FIG. 7 shows the gate of the sense amplifier output level correcting MOSFET when the power supply voltage V _CC fluctuates. Control voltage to be applied
It is explanatory drawing which shows an example of the characteristic of Vco. 1 ... CPU (microprocessor), 2 ... Rewritable memory (EPROM), 3 ... Random access memory, 4 ... Serial communication interface circuit, 7a ... Address bus, 7b ... Data bus,
9: Mode switching circuit, 11: Mode setting external terminal,
20a to 20h ... memory block, 21 ... dummy memory array, 24a to 24h ... column switch circuit, 25a to 25h ... read circuit, 26 ... dummy read circuit, 27 ... control circuit, 28a to 28h ... … Write circuit, 31 …… Level detection circuit, 32 …… Feedback circuit, 33 …… Wave shaping circuit (inverter), 34 …… Latch circuit (clocked inverter),
35 …… Output inverter, DL, DL _{1 to} DL ₈ …… Data line, D
Ld …… Dummy data line, Qc, Qc _{1 to} Qc ₈ …… Column switch, MC …… Memory cell, CS _{1 to} CS ₁₆ …… Common source line, C
DL, CDL _{1 to} CDL ₁₆ …… Common data line, Qw, Qw _{1 to} Qw ₈ …… Write control transistor.

Continuation of the front page (56) Reference JP-A-58-139393 (JP, A) JP-A-56-111190 (JP, A) JP-A-49-14052 (JP, A) JP-A-53-60125 (JP , A)

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising a CPU, a memory having a memory array and a peripheral circuit, and a control circuit for controlling the operation of the peripheral circuit, wherein the CPU has high-level periods with respect to each other. The first and second internal clock signals, which are out of phase with each other by a half cycle so as not to overlap with each other, have a frequency of 1/2 of these internal clock signals, and a time point substantially equal to the rising time point of the first clock signal. The semiconductor integrated circuit further includes a dummy memory array having dummy data lines and a read circuit for the dummy memory array, the clock generating circuit forming an external synchronizing signal that rises and falls at The peripheral circuit has a sense amplifier circuit connected to the data of the memory array and a latch circuit for receiving an output of the sense amplifier circuit. The troll circuit changes in the same manner in synchronization with the first clock signal only during the low level period of the external synchronizing signal to form a first signal for initializing the data line and the dummy data line to the low level. Means, a means for changing to a low level in synchronization with the fall of the first signal, and forming a second signal for precharging the data line and the dummy data line, and a fall of the second signal. And a means for forming a third signal for starting the precharge of the sense amplifier circuit and the read circuit of the dummy memory array in synchronism with the read signal of the dummy read circuit. The data is monitored, and when the data is confirmed, the signal that stops the read operation is output, and the control circuit outputs the output of the read circuit. The semiconductor integrated circuit read data, characterized by comprising adapted to output a control signal to the non-operating state the sense amplifier circuit after being latched in the latch circuit on the basis of the issue. 2. The semiconductor integrated circuit according to claim 1, wherein the memory is a rewritable memory composed of a non-volatile memory element. 3. The semiconductor integrated circuit according to claim 1, wherein the memory is a read-only memory in which a program necessary for system operation is stored.