JP4080043B2 - Booster circuit, semiconductor memory device, and data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge pump improvement technique, for example, a technique effective when applied to a flash memory and a microcomputer incorporating the same as a program memory.
[0002]
[Prior art]
Conventionally, nonvolatile semiconductor memory elements (memory cells) are arranged in an array, and the memory cells are electrically rewritten (electrically erased) in the memory cell group (sector) connected to the control gate common line, that is, the same word line. In a non-volatile memory that performs (electrical writing), a method has been proposed that enables erasing in units of word lines by applying a positive or negative high voltage to the word lines. This is described in, for example, “Symposium on VLSI Technology Digest of Technical Papers pp 77-78 1991” and “Symposium on VLSI Circuits Digest of Technical Papers pp 85-86 1991”. In such a semiconductor memory device, the high potential side power supply Vcc level supplied from the outside is boosted by a booster circuit to obtain a high voltage supplied to the internal circuit. A charge pump is applied to the booster circuit. Japanese Patent Laid-Open No. 8-149801 discloses a charge pump.
[0003]
[Problems to be solved by the invention]
In the charge pump, for example, as shown in FIG. 11, three diode-connected n-channel MOS transistors (in this case, depletion type) 11, 12, and 13 are connected in series, and a charge pump capacitor is connected to the series connection node. CpR1 and CpR2 are connected, and voltages Vc1 and Vc2 are supplied in pulses to the other ends of the charge pump capacitors CpR1 and CpR2, respectively, so that a boosted voltage VccR is obtained at the terminal of the smoothing capacitor CsR.
[0004]
In order to keep the level of the high voltage output from the charge pump constant, the level of the high voltage output from the charge pump is detected and compared with a reference voltage, and the charge pump is operated based on the comparison result. I have control. That is, when the level of the high voltage output from the charge pump exceeds a predetermined value, the switching operation of the charge pump is stopped by stopping the clock supply to the charge pump.
[0005]
However, when a charge pump is formed using a depletion type MOS transistor in order to increase the capacity of the booster circuit, when the charge pump switching is stopped, the charge flows backward between the capacitors, and the charge transfer efficiency deteriorates. Current consumption increases. For this reason, ripples (voltage fluctuations) are likely to occur, and the high voltage level may be undesirably lowered.
[0006]
An object of the present invention is to reduce power consumption of a booster circuit including a charge pump.
[0007]
Another object of the present invention is to provide a technique for reducing output voltage ripple.
[0008]
Another object of the present invention is to provide a semiconductor memory device including the booster circuit and a data processing device incorporating the semiconductor memory device.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
That is, when the booster circuit is configured to include the charge pumps (20A, 20B) for boosting the input voltage and the smoothing capacitor (C) for smoothing the output voltage of the charge pump, Based on the comparison circuit (50A, 50B) for comparing the output voltage and the reference voltage, the conversion circuit (40A, 40B) for level conversion of the comparison result of the comparison circuit, and the output signal of the conversion circuit, A backflow prevention circuit (31A, 31B) for preventing a current from flowing back to the output terminal of the charge pump is provided.
[0012]
According to the above means, the backflow prevention circuit prevents a current from flowing back to the output terminal of the charge pump based on the output signal of the conversion circuit. This achieves reduction in power consumption and ripple in the booster circuit including the charge pump.
[0013]
At this time, the backflow prevention circuit can be easily formed by a MOS transistor provided on a voltage transmission path formed by the charge pump.
[0014]
The charge pump includes a plurality of transistors (21 to 24, 91 to 94) connected in series to each other and a charge pump capacitor (C1 to C3) coupled to a series connection node of the plurality of transistors. In order to prevent backflow to the power supply side, a second backflow prevention circuit (32A, 32B) for preventing backflow to the power supply side is provided between the transistor and its power supply. Good.
[0015]
In order to prevent backflow between the charge pump capacitors, a third backflow prevention circuit (33A, 34A, 33B, 34B) for preventing backflow to the charge pump capacitors is provided between the plurality of transistors. Good.
[0016]
In a semiconductor memory device including internal boosting means for boosting the input voltage internally, and using the boosted output of the internal boosting means for write or erase operation, the boosting circuit (SUPP) described above is used as the internal boosting means. Can be applied.
[0017]
Furthermore, a data processing apparatus can be configured including such a semiconductor memory device (FMRY).
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 12 shows a single chip microcomputer which is an example of a data processing apparatus according to the present invention. The single chip microcomputer 10 shown in the figure includes a flash memory FMRY, a CPU 12, a DMAC 13, a bus controller (BSC) 14, a ROM 15, a RAM 16, a timer 17, a serial communication interface (SCI) 18, and first to ninth input / output ports. Functional blocks or modules of the IOP1 to IOP9 and the clock generator (CPG) 19 are formed as a semiconductor integrated circuit on one semiconductor substrate by a known semiconductor manufacturing technique.
[0019]
The single-chip microcomputer 10 has a ground level terminal Vss, a power supply voltage level terminal Vcc as power supply terminals, and a reset terminal RES, a standby terminal STBY, a mode control terminal MODE, and clock input terminals EXTAL and XTAL as other dedicated control terminals. . They are external terminals.
[0020]
The single chip microcomputer 10 operates in synchronization with a system clock generated by the clock oscillator 9 based on a crystal resonator (not shown) connected to the clock input terminals EXTAL and XTAL. Alternatively, an external clock may be input to the EXTAL terminal. One period of the system clock is called one state.
[0021]
The functional blocks are connected to each other by an internal bus. The internal bus includes an address bus / data bus, a control bus including a read signal, a write signal, a bus size signal, and a system clock. The internal address bus includes IAB and PAB, and the internal data bus includes IDB and PDB. The IAB and IDB are connected to the flash memory FMRY, the CPU 12, the ROM 15, the RAM 16, the bus controller 14, and a part of the input / output ports IOP1 to IOP9. PAB and PDB are connected to bus controller 14, timer 17, SCI 18, and input / output ports IOP1 to IOP9. The IAB and PAB, and IDB and PDB are interfaced by the bus controller 14, respectively. Although not particularly limited, PAB and PDB are exclusively used for register access in the functional block to which they are connected.
[0022]
The input / output ports IOP1 to IOP9 are also used for input / output of external bus signals and input / output signals of the input / output circuit. These functions are selected and used according to the operation mode or software settings. The external address and the external data are connected to IAB and IDB through buffer circuits (not shown) included in these input / output ports, respectively. PAB and PDB are used for reading / writing internal registers such as the input / output port and the bus controller 14, and are not directly related to the external bus.
[0023]
When a system reset signal is applied to the reset terminal RES, the operation mode given by the mode control terminal MODE is taken in, and the single chip microcomputer (hereinafter simply referred to as a microcomputer) 10 is reset. The operation mode is not particularly limited, but determines whether the built-in ROM 15 is valid / invalid, the address space is 16 Mbytes or 1 Mbytes, and the initial value of the data bus width is 8 bits or 16 bits. If necessary, the mode control terminal MODE is a plurality of terminals, and the operation mode is determined by the combination of the input states to these terminals.
[0024]
When the reset state is released, the CPU 12 reads the start address and performs a reset exception process that starts reading an instruction from the start address. Although the start address is not particularly limited, it is assumed that the start address is stored in an area starting from address 0. Thereafter, the CPU 12 sequentially executes instructions from the start address.
[0025]
In the microcomputer 10, the flash memory FMRY appropriately stores user programs, tuning information, data tables, and the like. The ROM 15 is not particularly limited, but stores a system program such as an OS.
[0026]
Here, operation control of the flash memory FMRY by the CPU 12 will be described. The flash memory FMRY is coupled to the internal buses IAB and IDB and is accessible by the CPU 12 and the like. That is, the CPU 12 sets control information for the write / erase control register WEREG, supplies the control signal READ when supplying a read operation for reading data from the memory cell MC, supplies an address signal, and supplies write data. Control. The CPU 12 issues a read operation instruction for erase verification and write verification, and the CPU 12 verifies the read data.
[0027]
A reset instruction to the reset terminal RES is given from a reset circuit arranged on the system. The reset circuit (not shown) instructs a reset to the reset terminal RES based on a power-on reset, a pressing operation of a reset button arranged on a system (not shown), or an instruction from the microcomputer 10.
[0028]
Although not particularly limited, the microcomputer 10 is set to an operation mode that enables direct external access to the flash memory FMRY when the mode signal MODE composed of a plurality of bits is set to a predetermined value. In this operation mode, the CPU 12 stops the substantial control operation to the outside or the connection between the CPU 12 and the internal buses IDB and IAB is disconnected, and the flash memory FMRY can be directly accessed from the outside through, for example, the input / output ports IOP1 and IOP2. Is done. In this operation mode, the microcomputer is equivalent to a single chip of the apparent flash memory FMRY. Therefore, all the access control information for the flash memory FMRY is supplied from an external data processor (not shown).
[0029]
Therefore, the operation of first writing a program or data to the flash memory FMRY built in the microcomputer 10 is performed efficiently by using a writing device such as an EPROM writer, or by the control of the built-in CPU 12. can do. The latter means that rewriting is possible even when the microcomputer is mounted on the circuit board (on-board state).
[0030]
FIG. 13 shows a configuration example of the flash memory FMRY. The flash memory FMRY shown in the figure has 8-bit data input / output terminals D0 to D7, and includes a memory array ARY0 to ARY7 for each data input / output terminal. Each of the memory arrays ARY0 to ARY7 is configured in the same manner, thereby forming one memory cell array.
[0031]
Each of the memory arrays ARY0 to ARY7 has a memory cell group SM in which memory cells each constituted by an insulated gate field effect transistor having a two-layer gate structure are arranged in a matrix.
[0032]
In the figure, W11 to Wij are word lines common to all the memory arrays ARY0 to ARY7. The control gates of the memory cells arranged in the same row are connected to the corresponding word lines.
[0033]
The source line SL is supplied with a high voltage Vpp used for erasing from a voltage output circuit VOUT such as an inverter circuit. The output operation of the voltage output circuit VOUT is controlled by an erase signal ERASE * (signal * indicates signal inversion or low enable) output from the erase control circuit ECONT. That is, during the low level period of the erase signal ERASE *, the voltage output circuit VOUT supplies the high voltage Vpp to the source line SL and supplies the high voltage necessary for erasure to the source regions of all the memory cells MC. As a result, the entire flash memory FMRY can be erased collectively.
[0034]
The selection of the word lines W11 to Wij is performed by the X address decoder XADEC decoding the X address signal AX taken in via the X address latch XALAT. The word driver WDRV drives the word line based on the selection signal output from the X address decoder XADEC. In the data read operation, the word driver WDRV is operated using a voltage Vcc such as 3V supplied from the voltage selection circuit VSEL and a ground potential such as 0V as power supplies, and the word line to be selected is set to a selected level by the voltage Vcc. The word line to be deselected is driven and maintained at a non-selected level such as a ground potential. In the data write operation, the word driver WDRV is operated using a voltage Vpp such as −9V and a ground potential such as 0V as power supplies, and drives a word line to be selected to a high voltage level for writing such as −9V. To do. In the data erasing operation, the output of the word driver WDRV is 9V.
[0035]
9V (or -9V) or the like output from the word driver WDRV or the like is generated by being boosted by the booster circuit SUPP and supplied to the voltage selection circuit VSEL or the voltage output circuit VOUT. The booster circuit SUPP will be described in detail later.
[0036]
In each of the memory arrays ARY0 to ARY7, the data lines DL0 to DL7 are commonly connected to a common data line CD via Y selection switches YS0 to YS7. Switch control of the Y selection switches YS0 to YS7 is performed by the Y address decoder YADEC decoding the Y address signal AY fetched through the Y address latch YALAT. The output selection signal of the Y address decoder YADEC is supplied in common to all the memory arrays ARY0 to ARY7. Accordingly, when any one of the output selection signals of the Y address decoder YADEC is set to the selection level, one data line is connected to the common data line CD of each of the memory arrays ARY0 to ARY7.
[0037]
Data read from the memory cell MC to the common data line CD is applied to the sense amplifier SA via the selection switch RS, where it is amplified and output to the data bus via the data output buffer DOB. The selection switch RS is switch-controlled by a read signal READ.
[0038]
Write data supplied from the outside is held in the data input latch DIL via the data input buffer DIB. When the data held in the data input latch DIL is “0”, the write circuit WR supplies a high voltage for writing to the common data line CD via the selection switch WS. The high voltage for writing is supplied to the drain of the memory cell to which the high voltage is applied to the control gate by the word line through one of the data lines selected by the Y selection switches YS0 to YS7. Is done. The selection switch WS is switch-controlled by a control signal WRITE. The write control circuit WCONT controls write operation procedures such as various timings of write and voltage selection control. A write / erase control register WEREG gives a write operation instruction and a write verify operation instruction to the write control circuit WCONT, and an erase operation instruction and an erase verify operation instruction to the erase control circuit ECONT. The control register WEREG can be connected to a data bus, and control data can be written from the outside.
[0039]
The control register WEREG has a Vpp bit, a PV bit, a P bit, and an E bit. The P bit is used as an instruction bit for the write operation. The E bit is an instruction bit for the erase operation. When the Vpp bit and the E bit are set, the erase control circuit ECONT that refers to the bit controls the internal operation for erasing according to a predetermined procedure. In addition, when the Vpp bit and the P bit are set, the write control circuit WCONT referring to them controls the internal operation for writing according to a predetermined procedure. Internal operations for erasing and writing are performed by generating a predetermined level of voltage. In the erase verify operation, a read operation is performed on the erased memory cell to verify whether or not the erase is completed, and the write verify operation reads the write data from the written memory cell and writes it. The operation is to verify whether or not the writing is completed by comparing with the data. These verify operations are performed when an external CPU or data processor starts a read cycle for the flash memory.
[0040]
FIG. 1 shows a configuration example of the booster circuit SUPP.
[0041]
The circuit shown in FIG. 1 is a circuit that boosts a positive high voltage based on a high-potential-side power supply Vcc. Basically, a charge pump 20A for boosting an input voltage by a switching operation, the charge pump 20A A backflow prevention circuit 31A for preventing a current from flowing back into the comparator 50A for comparing the output VccR of the booster circuit SUPP and the reference voltage Vref, and the comparison result of the comparison circuit 50A is level-converted. And a level conversion circuit 40A for generating a control signal for the backflow prevention circuit 31A.
[0042]
The charge pump 20A is configured as follows.
[0043]
Diode-connected n-channel MOS transistors (in this case, depletion type) 21, 22, 23, 24 are connected in series, and charge pump capacitors C1, C2, C3 are coupled to the series connection nodes of the MOS transistors. The high potential side power supply Vcc is supplied to one end of the n-channel MOS transistor 21.
[0044]
On the other hand, a NAND gate 25 for obtaining the NAND logic of the clock signal CLK, the booster circuit control signal CNTN, and the output signal of the comparison circuit 50A is provided, and inverters 26 to 30 for signal inversion are provided at the subsequent stage. Has been placed. Inverters 26, 27 and 28 are interposed between the NAND gate 25 and the charge pump capacitor C1, and inverters 26 and 29 are interposed between the NAND gate 25 and the charge pump capacitor C2. From the NAND gate 25 to the charge pump capacitor C3. Inverters 26, 27, and 30 are interposed between the two.
[0045]
The backflow prevention circuit 31A is not particularly limited, but is formed by one p-channel MOS transistor as shown in FIG. The drain electrode d of the p-channel MOS transistor is coupled to the output terminal of the charge pump 20A, and the source electrode s is coupled to the output line of the booster circuit SUPP. Further, the substrate N-Well is coupled to the source electrode s. An output voltage of the level conversion circuit 40A is supplied to the gate electrode g, and on / off control is performed by the output voltage of the level conversion circuit 40A. FIG. 2B shows a cross section of a p-channel MOS transistor forming the backflow prevention circuit 31A.
[0046]
The level conversion circuit 40A is formed by combining p-channel MOS transistors 41 and 43 and n-channel MOS transistors 42 and 44. A p-channel MOS transistor 41 and an n-channel MOS transistor 42 are connected in series, and a p-channel MOS transistor 43 and an n-channel MOS transistor are connected in series. The source electrodes of the p-channel MOS transistors 41 and 43 are coupled to the output line of the booster circuit SUPP. A series connection node of the p-channel MOS transistor 41 and the n-channel MOS transistor 42 is coupled to the gate electrode of the p-channel MOS transistor 43 and to the gate electrode of the MOS transistor forming the backflow prevention circuit 31A. The A series connection node of p-channel MOS transistor 43 and n-channel MOS transistor 44 is coupled to the gate electrode of p-channel MOS transistor 41. The source electrodes of the n-channel MOS transistors 42 and 44 are coupled to the ground line (Vss line).
[0047]
The comparison circuit 50A is configured as follows.
[0048]
Resistors r1 and r2 are connected in series to detect the level of the output voltage VccR of the booster circuit SUPP. The other end of the resistor r1 is coupled to the output line of the booster circuit SUPP, and the voltage Vn at the series connection node of the resistors r1 and r2 is applied to the gate electrode of the n-channel MOS transistor 55. This voltage Vn is expressed by the following equation.
[0049]
Vn = VccR · r2 / (r1 + r2)
An n-channel MOS transistor 55 and an n-channel MOS transistor 57 are differentially coupled. The source electrodes of the n-channel MOS transistors 55 and 57 are connected to the ground line (Vss line) via the n-channel MOS transistor 58. The drain electrodes of the n-channel MOS transistors 55 and 57 are coupled to the high potential side power source Vcc via the p-channel MOS transistors 55 and 57, respectively. A p-channel MOS transistor 53 is connected in parallel to the p-channel MOS transistor 54. A booster circuit control signal CNTN is input to the gate electrode of the p-channel MOS transistor 53 and the gate electrode of the n-channel MOS transistor 58. When the booster circuit control signal CNTN is set to the high level, the n-channel MOS transistor 58 is turned on and the p-channel MOS transistor 53 is turned off. A comparison is made. That is, the reference voltage Vref is supplied to the gate electrode of the n-channel MOS transistor 57, and the voltage (voltage division level) at the series connection node of the resistors r1 and r2 is supplied to the gate electrode of the n-channel MOS transistor 55. Thus, the voltage (voltage division level) Vn of the series connection node of the resistors r1 and r2 is compared with the reference voltage Vref. The logic level of the series connection node of the p-channel MOS transistor 54 and the n-channel MOS transistor 55 is transmitted via the inverter 52 to the gate electrode of the n-channel MOS transistor 44 in the level conversion circuit 40A. This signal is denoted CT1. Further, the signal CT1 is inverted by the inverter 51 at the subsequent stage and then transmitted to the gate electrode of the n-channel type MOS transistor 42 in the level conversion circuit 40A. This signal is CT2.
[0050]
Next, the operation will be described.
[0051]
FIG. 9 shows the operation timing of the main part in the booster circuit shown in FIG.
[0052]
When the booster circuit control signal CNTN is at a low level, the NAND gate 25 is inactivated, so that the clock signal CLK is not transmitted to the charge pump and the charge pump 20A is not operated. At this time, the n-channel MOS transistor 58 is turned off and the p-channel MOS transistor 53 is turned on, so that the comparison operation is stopped.
[0053]
When the booster circuit control signal CNTN is set to the high level, the charge pump 20A is operated in synchronization with the clock signal CLK, and the output voltage of the charge pump 20A is transmitted to the smoothing capacitor C. As a result, the output voltage VccR of the booster circuit SUPP and the divided voltage Vn of the resistors r1 and r2 are increased. When the divided voltage Vn of the resistors r1 and r2 is lower than the reference voltage Vref (Vn <Vref), the output signal CT1 of the inverter 52 is at a low level and the output signal CT2 of the inverter 51 is at a high level. At this time, the output signal of the level conversion circuit 40A is set to the low level, and the MOS transistor forming the backflow prevention circuit 31A is turned on.
[0054]
When the output voltage VccR of the booster circuit SUPP and the divided voltage Vn of the resistors r1 and r2 are increased by the operation of the charge pump 20A and the divided voltage Vn of the resistors r1 and r2 becomes higher than the reference voltage Vref (Vn> Vref). ), The output signal CT1 of the inverter 52 is at a high level, and the output signal CT2 of the inverter 51 is at a low level. When the output signal CT2 of the inverter 51 is set to the low level, the NAND gate 25 is deactivated and the operation of the charge pump 20A is stopped. Further, when the output signal CT2 of the inverter 51 is set to the low level, the output signal of the level conversion circuit 40A is set to the high level, and the MOS transistor forming the backflow prevention circuit 31A is turned off, so that the output voltage VccR Charge is prevented from flowing back to the charge pump 20A. For this reason, current consumption of the output voltage VccR is suppressed, and the efficiency of the booster circuit 20A can be improved. In addition, voltage drop (ripple) due to the backflow to the charge pump 20A can be reduced, and the power source for driving the word line of the memory circuit can be stabilized.
[0055]
FIG. 3 shows a circuit configuration for boosting a negative high voltage based on the low potential side power supply Vss. The circuit shown in FIG. 3 basically includes a charge pump 20B for boosting an input voltage (ground level) by a switching operation, and a backflow prevention circuit for preventing a current from flowing back to the charge pump 20B. 31B, the comparison circuit 50B for comparing the output VccM of the booster circuit SUPP and the reference voltage (ground level), and the comparison result of the comparison circuit 50B is level-converted to generate a control signal for the backflow prevention circuit 31B. And a level conversion circuit 40B.
[0056]
The charge pump 20B is configured as follows.
[0057]
Diode-connected p-channel MOS transistors (depletion type in this case) 91, 92, 93, 94 are connected in series, and charge pump capacitors C1, C2, C3 are coupled to the series connection nodes of the MOS transistors. A low potential side power supply Vss is supplied to one end of the p-channel MOS transistor 91.
[0058]
On the other hand, a NAND gate 25 for obtaining the NAND logic of the clock signal CLK, the booster circuit control signal CNTN, and the output signal of the comparison circuit 50B is provided, and inverters 26 to 30 for signal inversion are provided in the subsequent stage. Has been placed. Inverters 26, 27 and 28 are interposed between the NAND gate 25 and the charge pump capacitor C1, and inverters 26 and 29 are interposed between the NAND gate 25 and the charge pump capacitor C2. From the NAND gate 25 to the charge pump capacitor C3. Inverters 26, 27, and 30 are interposed between the two.
[0059]
The backflow prevention circuit 31B is not particularly limited, but is formed by one n-channel MOS transistor as shown in FIG. The drain electrode d of the n-channel MOS transistor is coupled to the output line of the charge pump 20B, and the source electrode S is coupled to the output terminal of the booster circuit SUPP. Further, the substrate P-Well is coupled to the source electrode s. An output voltage of the level conversion circuit 40B is supplied to the gate electrode, and on / off control is performed by the output voltage of the level conversion circuit 40B. FIG. 4B shows a cross section of an n-channel type MOS transistor forming the backflow prevention circuit 31B.
[0060]
The level conversion circuit 40B is formed by coupling p-channel MOS transistors 41 and 43 and n-channel MOS transistors 42 and 44. A p-channel MOS transistor 41 and an n-channel MOS transistor 42 are connected in series, and a p-channel MOS transistor 43 and an n-channel MOS transistor are connected in series. The source electrodes of the p-channel MOS transistors 41 and 43 are coupled to the high potential side power supply Vcc. A series connection node of the p-channel MOS transistor 41 and the n-channel MOS transistor 42 is coupled to the gate electrode of the n-channel MOS transistor 44 and to the gate electrode of the MOS transistor forming the backflow prevention circuit 31B. The A series connection node of p-channel MOS transistor 43 and n-channel MOS transistor 44 is coupled to the gate electrode of n-channel MOS transistor 42. The source electrodes of the n-channel MOS transistors 42 and 44 are coupled to the output line of the booster circuit SUPP.
[0061]
The comparison circuit 50B is configured as follows.
[0062]
Resistors r1 and r2 are connected in series in order to detect the level of the output voltage VccM of the booster circuit SUPP. The other end of the resistor r1 is coupled to the high potential side power supply Vcc, and the other end of the resistor r2 is coupled to the output line of the booster circuit SUPP. The voltage Vn at the series connection node of the resistors r1 and r2 is applied to the gate electrode of the p-channel MOS transistor 61. This voltage Vn is expressed by the following equation.
[0063]
Vn = (Vcc−VccM) · r2 / (r1 + r2)
A p-channel MOS transistor 61 and a p-channel MOS transistor 64 are differentially coupled. The source electrodes of the p-channel MOS transistors 61 and 64 are connected to the high potential side power source Vcc via the p-channel MOS transistor 62. The drain electrodes of the p-channel MOS transistors 61 and 64 are coupled to the low potential power source Vss via the n-channel MOS transistors 63 and 65, respectively. An n-channel MOS transistor 68 is connected in parallel to the n-channel MOS transistor 63, and a booster circuit control signal CNTN is transmitted to the gate electrode of the n-channel MOS transistor 68 via an inverter 67. The gate electrode of the p-channel MOS transistor 64 is set to the low potential side power supply Vss (ground) level, which is used as a reference voltage in the comparison operation. When the booster circuit control signal CNTN is at the high level, the output of the inverter 67 is set to the low level, and the voltage (divided level) Vn and the reference voltage (low potential) at the series connection node of the resistors r1 and r2 in the comparison circuit 50B. Side power supply Vss).
[0064]
The logic level of the serial connection node of the p-channel MOS transistor 61 and the n-channel MOS transistor 63 is transmitted to the gate electrode of the p-channel MOS transistor 43 in the level conversion circuit 40B as the signal CT2 via the inverter 52. And transmitted to the input terminal of the NAND gate 25. Further, the output signal of the inverter 52 is inverted by the inverter 51 in the subsequent stage, and then transmitted as the signal CT1 to the gate electrode of the p-channel MOS transistor 41 in the level conversion circuit 40B.
[0065]
Next, the operation will be described.
[0066]
FIG. 10 shows the operation timing of the main part in the booster circuit shown in FIG.
[0067]
When the booster circuit control signal CNTN is at a low level, the NAND gate 25 is inactivated, so that the clock signal CLK is not transmitted to the charge pump and the charge pump 20B is not operated. At this time, the n-channel MOS transistor 68 is turned on, and the input terminal of the inverter 52 is fixed at a low level.
[0068]
When the booster circuit control signal CNTN is set to the high level, the charge pump 20B is operated, whereby the output voltage VccM of the booster circuit SUPP and the divided voltage Vn of the resistors r1 and r2 are increased. When the divided voltage Vn of the resistors r1 and r2 is higher than the low potential side power supply Vss, the signal CT1 becomes low level and the signal CT2 becomes high level, and the n-channel MOS transistor forming the backflow prevention circuit 31B is turned on. The output voltage of the charge pump 20B is transmitted to the smoothing capacitor C. When the divided voltage Vn of the resistors r1 and r2 is lower than the low potential side power source Vss, the signal CT1 output from the inverter 51 is at a high level and the signal CT2 output from the inverter 52 is at a low level. When the signal CT2 is set to the low level, the NAND gate 25 is deactivated, and the operation of the charge pump 20B is stopped. At this time, the n-channel MOS transistor forming the backflow prevention circuit 31B is turned off to prevent backflow.
[0069]
As described above, when the signal CT2 output from the inverter 52 is set to the low level, the NAND gate 25 is deactivated and the operation of the charge pump 20B is stopped. Since the type MOS transistor is turned off and the reverse flow is prevented, the current consumption of the output voltage VccM is suppressed, and the efficiency of the booster circuit 20B can be improved. In addition, voltage drop (ripple) due to backflow to the charge pump 20B can be reduced, and the power supply for driving the word line of the memory circuit can be stabilized.
[0070]
In addition, by reducing the current consumption of the booster circuit SUPP as described above, it is possible to reduce the current consumption of the flash memory FMRY including the booster circuit SUPP, and further to reduce the current consumption of the microcomputer 10 including the same.
[0071]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0072]
In FIG. 5, a backflow prevention circuit 32 </ b> A is provided between the high-potential side power supply Vcc and the n-channel MOS transistor 21 in the configuration shown in FIG. 1. Similar to the backflow prevention circuit 31A, the backflow prevention circuit 32A can be formed by a p-channel MOS transistor, and is controlled to be turned on / off in conjunction with the p-channel MOS transistor forming the backflow prevention circuit 31A. When the backflow prevention circuit 31A is turned off, the backflow prevention circuit 32A is also turned off. When the backflow prevention circuit 32A is turned off, the high potential side power supply Vcc and the n-channel MOS transistor 21 are separated, so that backflow to the high potential side power supply Vcc side can be prevented.
[0073]
The circuit shown in FIG. 6 is obtained by further adding backflow prevention circuits 33A and 34A to the configuration shown in FIG.
[0074]
The backflow prevention circuit 33A is provided between the n-channel MOS transistor 22 and the n-channel MOS transistor 23, and the backflow prevention circuit 34A is provided between the n-channel MOS transistor 23 and the n-channel MOS transistor 24. It is done. The backflow prevention circuits 33A and 34A are p-channel MOS transistors similarly to the backflow prevention circuits 31A and 32A, respectively, and are driven simultaneously by the output signal of the level conversion circuit 40A. In such a configuration, a backflow prevention circuit 33A is provided between the n-channel MOS transistor 22 and the n-channel MOS transistor 23, and a backflow prevention circuit 34A is provided between the n-channel MOS transistor 23 and the n-channel MOS transistor 24. Are provided and are turned off, so that backflow between the charge pump capacitors C1, C2, and C3 can be prevented. That is, the accumulated charge state of the charge pump capacitors C1, C2, and C3 can be maintained from when the charge pump 20A is stopped until the next operation. For this reason, the rise when the charge pump 20A is stopped and then operated next is quickened.
[0075]
In FIG. 7, in contrast to the configuration shown in FIG. 3, a backflow prevention circuit 32 </ b> B is also provided between the low potential side power supply Vss and the p-channel MOS transistor 91. Similarly to the backflow prevention circuit 31B, the backflow prevention circuit 32B can be formed by an n-channel MOS transistor, and is controlled to be turned on and off in conjunction with the n-channel MOS transistor forming the backflow prevention circuit 31B. When the backflow prevention circuit 31B is turned off, the backflow prevention circuit 32B is also turned off. By turning off the backflow prevention circuit 32B, the low potential side power supply Vss and the p-channel MOS transistor 91 are separated, so that backflow to the low potential side power supply Vss side can be prevented.
[0076]
The circuit shown in FIG. 8 is provided with backflow prevention circuits 33B and 34B in addition to the configuration shown in FIG.
[0077]
The backflow prevention circuit 33B is provided between the p-channel MOS transistor 92 and the p-channel MOS transistor 93, and the backflow prevention circuit 34B is provided between the p-channel MOS transistor 93 and the p-channel MOS transistor 94. It is done. The backflow prevention circuits 33B and 34B are n-channel MOS transistors similarly to the backflow prevention circuits 31B and 32B, respectively, and are driven simultaneously by the output signal of the level conversion circuit 40B. In such a configuration, the backflow prevention circuit 33B is provided between the p-channel MOS transistor 92 and the p-channel MOS transistor 93, and the backflow prevention circuit 34B is provided between the p-channel MOS transistor 93 and the p-channel MOS transistor 94. Are provided and are turned off, so that backflow between the charge pump capacitors C1, C2, and C3 can be prevented. That is, the accumulated charge state of the charge pump capacitors C1, C2, and C3 can be maintained from when the charge pump 20B is stopped until it is next operated. For this reason, when the charge pump 20B is stopped, the next operation is accelerated.
[0078]
In the above description, the case where the invention made by the present inventor is applied to the flash memory, which is the field of use behind it, has been described. However, the present invention is not limited to this and requires a high voltage. The present invention can be widely applied to semiconductor integrated circuits and data processing devices including the same.
[0079]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0080]
In other words, by providing a backflow prevention circuit, it is possible to prevent a current from flowing back to the charge pump, so that the power consumption of the booster circuit including the charge pump can be reduced.
[0081]
By providing a backflow prevention circuit for preventing backflow to the power supply side between the transistor forming the charge pump and its power supply, backflow to the power supply side can be prevented.
[0082]
Further, by providing a backflow prevention circuit for preventing backflow to the charge pump capacitor between the plurality of transistors, backflow between the charge pump capacitors can be prevented.
[0083]
Since the power consumption of the booster circuit including the charge pump can be reduced as described above, the power consumption of the semiconductor integrated circuit and the data processing device including the booster circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first configuration example of a booster circuit included in a flash memory which is an example of a semiconductor memory device according to the present invention;
2 is a circuit diagram and a cross-sectional view of a MOS transistor applied as a backflow prevention circuit in the booster circuit shown in FIG.
FIG. 3 is a circuit diagram of a second configuration example of a booster circuit included in a flash memory which is an example of a semiconductor memory device according to the present invention.
4 is a circuit diagram and a cross-sectional view of a MOS transistor applied as a backflow prevention circuit in the booster circuit shown in FIG.
FIG. 5 is a circuit diagram showing another configuration example of the booster circuit.
FIG. 6 is a circuit diagram showing another configuration example of the booster circuit.
FIG. 7 is a circuit diagram showing another configuration example of the booster circuit.
FIG. 8 is a circuit diagram showing another configuration example of the booster circuit.
FIG. 9 is an operation timing chart of the main part in the booster circuit shown in FIG. 1;
10 is an operation timing chart of the main part of the booster circuit shown in FIG. 3;
FIG. 11 is a basic configuration of a charge pump and a waveform diagram of each part.
FIG. 12 is a block diagram illustrating a configuration example of a microcomputer including the flash memory.
FIG. 13 is a block diagram showing an example of the overall configuration of the flash memory.
[Explanation of symbols]
10 Microcomputer
12 CPU
13 DMAC
14 BSC
15 ROM
16 RAM
17 Timer
18 SCI
19 CPG
20A, 20B charge pump
31A, 31B, 32A, 32B, 33A, 33B, 34A, 34B Backflow prevention circuit
40A, 40B level conversion circuit
50A, 50B comparison circuit
FMRY flash memory
WDRV word driver

Claims (5)

In a booster circuit including a charge pump for boosting an input voltage and a smoothing capacitor for smoothing the output voltage of the charge pump,
A comparison circuit for comparing the output voltage of the charge pump with a reference voltage;
A conversion circuit for level-converting the comparison result of the comparison circuit;
A backflow prevention circuit for preventing backflow of current to the charge pump based on an output signal of the conversion circuit;
2. The booster circuit according to claim 1, wherein the backflow prevention circuit is a MOS transistor provided on a voltage transmission path formed by the charge pump.   When the charge pump includes a plurality of transistors connected in series to each other and a charge pump capacitor coupled to a series connection node of the plurality of transistors, between the transistor and its power supply, 2. The booster circuit according to claim 1, further comprising a second backflow prevention circuit for preventing backflow to the power supply side. 3. The booster circuit according to claim 2, wherein a third backflow prevention circuit for preventing backflow to the charge pump capacitor is provided between the plurality of transistors. In a semiconductor memory device including internal boosting means for boosting an input voltage internally, and using the boosted output of the internal boosting means for a write or erase operation,
4. A semiconductor memory device, wherein the boosting circuit according to claim 1 is applied as the internal boosting means.   5. A data processing apparatus formed on a single chip including a program memory and a central processing unit that executes a program stored in the program memory, and data obtained by applying the semiconductor memory device according to claim 4 as the program memory Processing equipment.

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