JPH07249979A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide the semiconductor integrated circuit with an output circuit capable of forming the output level according to the relatively low power supply voltage while keeping the high integration processing and high speed processing. CONSTITUTION:The output signal is obtained from the external terminal by switch-controlling the N-channel MOSFETs Q1 and Q2 connected in serial with the relatively low power supply voltage and the ground potential of the circuit. A driving signal to be supplied to the gate of the output MOSFET at the power supply voltage side is formed by a CMOS circuit consisting of MOSFETs Q3 and Q4. The operation voltage is boosted voltage using a bootstrap circuit. Thus, the high integration processing and the high speed processing are realized by using the N-channel MOSFET and the gate voltage of the output MOSFET Q1 which forms the output level at the power supply voltage side can be made high voltage corresponding to the boosted voltage. Thus, the output level can be made the one corresponding to the power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively used for an output circuit in a semiconductor integrated circuit device which is operated by a low voltage of about 3V or less.

[0002]

2. Description of the Related Art As an output circuit formed in a semiconductor integrated circuit device, there is an output circuit composed of an N-channel MOSFET or a CMOS circuit composed of a P-channel MOSFET and an N-channel MOSFET. On the other hand, there is a 3V system in addition to the general 5V system for low power consumption and high speed.

[0003]

In the semiconductor integrated circuit device of the 3V system, the high level of the output signal is determined to be 2.4V as in the 5V system. Therefore, if an N-channel MOSFET is formed into a source follower mode and a high-level output signal is to be formed, the level is lowered by the threshold voltage, and the high-level signal cannot be formed. On the other hand, P-channel MOS
CMOS consisting of FET and N-channel MOSFET
When an output circuit is used, a high level can obtain a sufficient level corresponding to the power supply voltage, but on the other hand, in order to obtain a drive current required to charge up a relatively large parasitic capacitance connected to an external terminal at high speed, P Channel type MOSFE
Not only does the size of T have to be increased, the integration becomes worse, but a latch-up measure peculiar to the CMOS circuit is required.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with an output circuit capable of forming an output level corresponding to a relatively low power supply voltage while achieving high integration and high speed. It is in. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, an N-channel MOSFET connected in series between a relatively low power supply voltage and the ground potential of the circuit is complementarily switch-controlled to obtain an output signal from an external terminal and an output on the power supply voltage side. M
The driving poetry supplied to the gate of the OSFET Q1 is CMOS
It is formed by a circuit, and its operating voltage is boosted using a bootstrap circuit.

[0006]

According to the above means, the N-channel type MOS
Since the gate voltage of the output MOSFET that forms the output level on the power supply voltage side can be set to a high voltage corresponding to the boosted voltage while using the FET to achieve high integration and high speed, the output level is set to the power supply voltage. It can be set to the corresponding level.

[0007]

1 is a schematic circuit diagram of an embodiment of an output circuit according to the present invention. The output circuit shown in the figure is formed on one semiconductor substrate such as a single-crystal Syringo by a known CMOS semiconductor integrated circuit manufacturing technique together with other internal circuits and input circuits. Although not particularly limited, a semiconductor integrated circuit device provided with the above output circuit,
The power supply voltage VCC is operated by a low voltage such as about 3V.

The output circuit is an N-channel MO connected in series between the power supply voltage VCC and the ground potential of the circuit.
It is composed of SFETs Q1 and Q2. The output MOSFET on the power supply voltage VCC side is a source follower output MOSFET.
It is operated as T. Therefore, when the drive signal supplied to the gate is set to a high level such as the power supply voltage VCC, the output signal obtained from the output terminal Dout becomes Vcc-.
The level is lowered by Vth (Vth is the threshold voltage of the MOSFET Q1). Therefore, when the power supply voltage VCC is a low voltage such as about 3V as described above, the high level of the output signal is only about 2V.

In this embodiment, the output M on the side of the power supply voltage is
A CMOS inverter circuit IV is used as a drive circuit for driving the OSFET Q1. This CMOS inverter circuit IV is a P-channel MOSFET as described later.
And N-channel MOSFET are connected in series,
A signal DO to be output is supplied with the gate common. Also, the output MOSFE on the ground potential side of the circuit
The signal DO is supplied to the gate of TQ2.

The CMOS inverter circuit IV is simply output M
With only the drive circuit of the OSFET Q1, the drive voltage supplied to the gate of the output MOSFET Q1 as described above can obtain only the level of the power supply voltage VCC. Therefore, in this embodiment, the operating voltage of the CMOS inverter circuit IV is boosted with respect to the power supply voltage VCC by the boosted voltage formed by the booster circuit to compensate for the level drop due to the output MOSFET Q1.

The booster circuit is composed of a charge pump circuit that receives the power supply voltage VCC and the timing signal DS.
A boosted voltage of + Vth or more is formed. As a result, when the signal DO to be output is low level, the output MOSFET Q2 is turned off by the low level of the signal DO.
The CMOS inverter circuit IV forms a high level drive signal according to the low level of the signal DO. This high-level drive signal is a boosted voltage VC which is its operating voltage.
It is set to a high level of C + Vth or higher. As a result, a high level such as the power supply voltage VCC is output from the source of the output MOSFET Q1. As a result, the output high level standard such as the low voltage interface specification of 2.4 V can be sufficiently satisfied.

FIG. 2 is a specific circuit diagram showing an embodiment of the output circuit according to the present invention. Each circuit element in the figure is
Similar to the embodiment shown in FIG. 1, it is formed on one semiconductor substrate such as single crystal silicon by the CMOS integrated circuit manufacturing technique.

Similarly to the above, the output MOSFET Q1 connected in series between the power supply voltage VCC and the ground potential of the circuit.
In the output circuit composed of Q2 and Q2, the inverted signal / DO to be output is supplied to the gate of the output MOSFET Q2 on the ground potential side of the circuit. A drive signal formed by a CMOS inverter circuit IV1 including a P-channel MOSFET Q3 and an N-channel MOSFET Q4 is supplied to the gate of the output MOSFET Q1 on the power supply voltage VCC side which is operated as a source follower. A similar CM is input to the input of the CMOS inverter circuit IV1.
The non-inverted signal DO to be output is supplied through the OS inverter circuit IV2. The CMOS inverter circuit I
V2 is operated by the power supply voltage VCC, while the CMOS inverter circuit IV1 as the drive circuit uses a boosted voltage formed by a booster circuit described below as an operating voltage.

The booster circuit is composed of the following circuits. The signal DO corresponds to the CMOS inverter circuit IV.
It is supplied to one electrode of the capacitor C1 via a CMOS inverter circuit IV3 similar to that of No. 2. The power supply voltage VCC is supplied to the other electrode of the capacitor C1 through a diode-type N-channel MOSFET Q6. That is, the gate of the MOSFET Q6 is connected to the power supply voltage VCC so that a current flows from the power supply voltage VCC to the boosting node N1 which is the other electrode of the capacitor C1.

A diode type N-channel MOSFET Q5 is provided to clamp the voltage of the boosting node N1 of the other electrode of the capacitor C1. That is, the diode-type MOSFET Q5 has a gate connected to the boosting node N1 so that a current flows from the boosting node N1 toward the power supply voltage VCC. Such a voltage clamp circuit is provided for the following reason.

The voltage boosted by the capacitor C1 is
It is supplied to the gate of the N-channel type MOSFET Q7. The MOSFET Q7 is provided for supplying the power supply voltage VCC to the other electrode of the capacitor C2 whose one electrode is supplied with the signal DO. This capacitor C
When the MOSFET Q6 connected in the diode form like the capacitor C1 is used, the charge voltage supplied to 2 becomes only a low potential like VCC-Vth.
On the other hand, by setting the voltage boosted by the capacitor C1 as described above, it is possible to charge up to the power supply voltage VCC. At this time, if the boosted voltage of the node N1 is set higher than VCC + Vth, the potential of the boosted node N2 due to the capacitor C2 is about 2.
This is because when the voltage rises to VCC, the MOSFET Q7 is turned on and the charge held in the capacitor C2 is discharged to the power supply voltage VCC side. That is, MO
By clamping the gate voltage of the SFET Q7 to VCC + Vth, when the boosted voltage is formed by the capacitor C2, the MOSFET Q7 is maintained in the off state and the voltage of the boosted node N2 is maintained high.

The voltage of the boosting node N2 is used as the operating voltage of the driving CMOS inverter circuit IV1. That is, the boosting node N2 is a P-channel type MO of the CMOS inverter circuit IV1 as a drive circuit.
It is supplied to the source of SFET Q3.

The operation of the circuit of this embodiment is as follows. As will be described later, the output terminal Dout is connected to the data bus, or the input terminal Din of the input circuit (not shown).
When used in common with the semiconductor integrated circuit device, in order to use the data bus for data transfer by another circuit when the semiconductor integrated circuit device is inactive, the output circuit is set to the output high impedance state or the input circuit is set to the operating state. It is necessary to bring the above output circuit into the output high impedance state also when the input signal is taken in. Therefore, the signals DO and / DO are both brought to a low level by the output control circuit (not shown) when brought into the output high impedance state as described above. The output MOSFET Q2 is turned off by the low level of the signal / DO. Further, depending on the low level of the signal DO, the inverter circuits IV2 and IV2
Since the low level is supplied to the gate of the output MOSFET Q1 through 1, the output MOSFET Q1 is also turned off.

Thus, when the output circuit is in a non-operating state, a low level such as the ground potential of the circuit is supplied to one electrode of the capacitor C2. On the other hand, at one electrode of the capacitor C1, the output of the inverter circuit IV3 becomes low level when the previous output is at high level, and the charge-up operation is performed on the capacitor C1 through the MOSFET Q6. The potential of the node N1 is boosted to VCC + Vth according to the low level of DO. As a result, the capacitor C1 becomes a MOSFET
It is charged up to the power supply voltage VCC through Q7.

When the signal DO is set to the high level by the output control circuit, the other voltage of the capacitor C2 becomes about 2V.
It is boosted to CC. The high level of the signal DO causes the output signal of the inverter circuit IV2 to go low, turning on the P-channel MOSFET Q3. As a result, the voltage of 2VCC is transmitted to the gate of the output MOSFET Q1. By appropriately selecting the ratio of the capacitance value of the capacitor C2 and the gate capacitance value of the MOSFET Q1, the gate voltage of the MOSFET Q1 can be set to VC.
It can be C + Vth or more. In this way, M
The level of the output signal Dout formed through the OSFET Q1 can sufficiently satisfy the power supply voltage VCC or the high level standard 2.4V of the low voltage interface specification of the CMOS semiconductor integrated circuit.

In this embodiment, as described above, the output MOS
Since the FET is formed by N-channel type MOSFETs Q1 and Q2, the source of the MOSFET Q1 and the MOS
The drain of the FET Q2 can be formed by a common diffusion layer, and a P-channel M that is made large to obtain a large current as in the case of using a CMOS circuit.
The P-channel MOSFET and the N-channel MOS are formed so that the OSFET is not formed in the well different from the N-channel MOSFET or the parasitic thyristor element that causes CMOS latch-up is not turned on.
Since the FET and the FET are not formed separately from each other, the output circuit can be configured with a small occupied area.

In the circuit of this embodiment, a booster circuit is required for output level compensation, but these circuit elements can be constructed in a very small size as compared with the output MOSFETs Q1 and Q2, and as described above. Since the area occupied by the output circuit itself is small, the area occupied by the output buffer including the output control circuit can be greatly reduced as compared with the case where a CMOS circuit is used.

FIG. 3 shows a block diagram of an embodiment of the synchronous DRAM (hereinafter, simply referred to as SDRAM) to which the present invention is applied. S shown in the figure
The DRAM is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known CMOS semiconductor integrated circuit manufacturing technique. SDR of this embodiment
The AM also has a low operating voltage of about 3V.

The SDRAM of this embodiment includes a memory array 200A forming a memory bank A (BANKA),
Memory array 2 forming a memory bank (BANKB)
With 00B. Each memory array 200A and 2
00B includes dynamic memory cells arranged in a matrix, and according to the drawing, the selection terminals of the memory cells arranged in the same column are coupled to word lines (not shown) for each column,
Data input / output terminals of memory cells arranged in the same row are coupled to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to the selection level according to the result of decoding the row address signal by the row decoder 201A. The complementary data line (not shown) of the memory array 200A is coupled to the sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell. The column switch circuit therein is a switch circuit for individually selecting complementary data lines and bringing them into conduction with the complementary common data line 204. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A. Similarly, the row decoder 201 is also provided on the memory array 200B side.
B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are provided.

The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are connected to 16-bit data input / output terminals I / O0 to I / O15. The output buffer 211 has 16 output circuits corresponding to the data input / output terminals I / O0 to I / O15, each of which is composed of the circuit as shown in FIG. 1 or 2. In the case where the external terminal is used as the input terminal or the output terminal according to the operation mode as in this embodiment, the output circuit has a three-state output including a high level / low level signal output and an output high impedance. It has a function. Therefore, the output MOSFET Q1 of FIG. 1 or FIG.
And Q2 are brought into an output high-impedance state in which both MOSFETs Q1 and Q2 are in an off state by the output control signal except in the output operation.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are fetched in the column address buffer 205 and the row address buffer 206 in the address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal. The output of the column address buffer 205 is supplied as preset data of the column address counter 207, and the column address counter 207 determines the column address signal as the preset data or the column address thereof according to the operation mode specified by a command or the like described later. The value obtained by sequentially incrementing the signal is output to the column decoders 203A and 203B.

The controller 212 is not particularly limited, but the clock signal CLK and the clock enable signal CK.
E, chip select signal / CS, column address strobe signal / CAS (symbol / means that the signal with this symbol is a row enable signal), row address strobe signal / RAS, write enable signal / WE, etc. External control signal and address input terminal A0
The control data from A9 is supplied to form an internal timing signal for controlling the operation mode of the SDRAM and the operation of the above circuit block on the basis of the change in the level of these signals and the timing. It includes a logic (not shown) and a mode register 30.

The clock signal CLK is used as the SDRAM clock, and other external input signals are significant in synchronization with the rising edge of the clock signal CLK. The chip select signal / CS instructs the start of a command input cycle by its low level. When the chip select signal / CS is at high level (chip non-selected state), other inputs have no meaning. However, a selected state of a memory bank and an internal operation such as a burst operation, which will be described later, are not affected by the change to the chip non-selected state. /
The RAS, / CAS, and / WE signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
When E is high level, the next rising edge of the clock signal CLK is valid, and when it is low level, it is invalid. Further, although not shown, in the read mode, an external control signal for controlling the output enable for the output buffer 211 is also supplied to the controller 212, and when the signal is at a high level, for example, in FIG.
Alternatively, an output buffer 211 including an output circuit as shown in FIG.
Is placed in a high output impedance state.

The row address signal is the clock signal C.
It is defined by the levels of A0 to A8 in a row address strobe / bank active command cycle described later that is synchronized with the rising edge of LK. The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is low level, the memory bank BANKA is selected, and when the input of A9 is high level, the memory bank BANKB is selected. Memory bank selection control is
Although not particularly limited, processing such as activation of only the row decoder on the selected memory bank side, non-selection of all column switch circuits on the unselected memory bank side, connection to the input buffer 210 and output buffer 211 on the selected memory bank side only, etc. Can be done by

The input of A8 in a precharge command cycle, which will be described later, indicates the mode of precharge operation for the complementary data lines and the like, and its high level indicates that the precharge targets are both memory banks, and its low level. Indicates that one of the memory banks designated by A9 is to be precharged.

The column address signal is A0 in a read or write command (column address read command, column address write command to be described later) cycle synchronized with the rising edge of the clock signal CLK.
~ Defined by A7 level. The column address thus defined is used as the start address for burst access.

Next, the SDR designated by the command
The main operation modes of the AM will be described. (1) Mode register set command (Mo) This is a command for setting the mode register 30 and is data specified by / CS, / RAS, / CAS, / WE = low level, and data to be set (register set data). ) Is given via A0-A9. The register set data is not particularly limited,
Burst length, CAS latency, write mode, etc. Although not particularly limited, burst lengths that can be set are 1, 2, 4, 8, and full page (256).
The settable CAS latencies are 1, 2 and 3, and the settable write modes are burst write and single write.

The CAS latency is the output buffer 21 from the fall of / CAS in the read operation instructed by the column address read command described later.
This is to instruct how many cycles of the clock signal CLK are spent until the output operation of 1. An internal operation time for reading the data is required until the read data is determined, and this is for setting it according to the frequency used of the clock signal CLK. In other words, the CAS latency is set to a relatively large value when the high frequency clock signal CLK is used, and the CAS latency is set to a relatively small value when the low frequency clock signal CLK is used.

(2) Row address strobe / bank active command (Ac) This is a command for validating the row address strobe instruction and the memory bank selection by A9.
Instructed by S, / RAS = low level and / CAS, / WE = high level, the addresses supplied to A0 to A8 at this time are fetched as row address signals, and the signal supplied to A9 is fetched as a memory bank selection signal. .
The fetching operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is designated, the word line in the memory bank designated by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column address read command (Re) This command is a command necessary for starting the burst read operation and a command for giving a column address strobe, / CS, / CAS =
Instructed by low level, / RAS, / WE = high level, and the column address supplied to A0 to A7 at this time is fetched as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address. Before the burst read operation instructed by this, the memory bank and the word line in it are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is clocked by the clock signal CLK. In synchronism with, the column address counter 207 sequentially selects according to an address signal output from the column address counter 207 and continuously reads. The number of data read continuously is the number specified by the burst length. The data reading from the output buffer 211 is started after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

(4) Column address write command (Wr) When the burst write is set in the mode register 30 as a mode of the write operation, it is regarded as a command necessary to start the burst write operation, and the write operation is performed. As a mode, when the single write is set in the mode register 30, it is a command necessary for starting the single write operation. Further, the command gives an instruction of the column address strobe in single write and burst write. The command is / C
Instructed by S, / CAS, / WE = low level and / RAS = high level, the addresses supplied to A0 to A7 at this time are fetched as column address signals.
The column address signal thus fetched is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed by this is performed similarly to the burst read operation. However, for the write operation, CAS
There is no latency, and the acquisition of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a start command of the precharge operation for the memory bank selected by A8 and A9, and / C
Instructed by S, / RAS, / WE = low level and / CAS = high level.

(6) Auto-refresh command This command is a command required to start auto-refresh and is / CS, / RAS, / CA.
Instructed by S = low level and / WE, CKE = high level.

(7) Burst stop in full page command This command is necessary to stop the burst operation for full pages for all memory banks, and is ignored in burst operations other than full page. This command is / CS, / WE = low level, / RAS, / CA
S = Indicated by high level.

(8) No operation command (No
p) This is a command instructing not to perform a substantial operation, and / CS = low level, / RAS, / CAS, / W
Indicated by the high level of E.

In the SDRAM, when a burst operation is being performed in one memory bank, another memory bank is designated and a row address strobe / bank active command is supplied in the middle of the burst operation. It is possible to operate the row address system in the other memory bank without affecting the operation in the other memory bank. For example, the SDRAM has means for internally holding data, an address and a control signal supplied from the outside, and the held contents, particularly the address and the control signal are not particularly limited, but may be held for each memory bank. It has become. Alternatively, the data for one word line in the memory block selected by the row address strobe / bank active command cycle is latched in advance by the latch circuit (not shown) for the read operation before the column operation. There is.

Therefore, the data input / output terminals I / O0 to I / O0
As long as the data does not collide in the I / O 15, a precharge command for a memory bank different from the memory bank to be processed by the command being executed, a row address strobe / bank active command, during command execution whose processing has not ended Can be issued to start the internal operation in advance.

Since the SDRAM 22 can input and output data, address, and control signals in synchronization with the clock signal CLK, it is possible to operate a large-capacity memory similar to the DRAM at a high speed comparable to that of the SRAM, and it is selected. By specifying the number of data to be accessed for one word line by the burst length, the built-in column address counter 207 sequentially switches the selected state of the column system to continuously output a plurality of data. It will be appreciated that it can be read or written.

In the SDRAM as described above, a large amount of data is continuously read out at a high speed like a burst read. Therefore, in the output circuit like the embodiment of FIG. Can work well,
Data can be output at high speed.

When the output circuit is inactive for a long time, the boosted voltage due to the capacitor C1 leaks and the first high level data output is delayed or the level is insufficient. In order to prevent the occurrence of the above, in the embodiment of FIG. 2, the inverter circuit IV3 is used as a CMOS gate circuit to supply one dummy pulse prior to the output operation so that the boosting operation of the capacitor C1 is performed. Good. Further, if the boosted voltage is constantly generated by the charge pump circuit by the pulse DS generated based on the clock pulse CLK input to the SDRAM as in the embodiment of FIG. Does not occur.

The operation and effect obtained from the above embodiment are as follows. (1) N-channel MOSFE connected in series between a relatively low power supply voltage and the ground potential of the circuit
T is complementarily switch-controlled to obtain an output signal from an external terminal, and a driving circuit supplied to the gate of the output MOSFET Q1 on the power supply voltage side is formed by a CMOS circuit, and its operating voltage is boosted using a bootstrap circuit. With this configuration, the gate voltage of the output MOSFET forming the output level on the power supply voltage side can be set to a high voltage corresponding to the boosted voltage while achieving high integration and high speed by using the N-channel MOSFET. Therefore, there is an effect that the output level can be set to a level corresponding to the power supply voltage.

(2) As a booster circuit, a signal to be output is supplied to one electrode through an inverter circuit, and the other electrode of a capacitor is charged through a diode-type N-channel first MOSFET. Formed by the second capacitor by charging up the second capacitor in response to the signal to be output through the MOSFET controlled by the boosted voltage formed by the first capacitor. By forming the operating voltage of the CMOS drive circuit by the boosted voltage, it is possible to form the boosted voltage when necessary according to the signal to be output, without providing a special timing pulse or control signal. The effect is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
Alternatively, the drive circuit of FIG. 2 may also have a logic gate function that creates an output high impedance state in which both output MOSFETs Q1 and Q2 are turned off. In the output buffer that does not require the output high impedance state as described above, the output MOSFET Q2 may be driven by the output signal of the CMOS inverter circuit IV2 in the embodiment of FIG. in this way,
The control circuit for controlling the output MOSFETs Q1 and Q2 can adopt various embodiments. The booster circuit may be any one as long as it uses the bootstrap or charge pump action of the capacitor as described above.

In addition to the SDRAM described above, the present invention is also applicable to DRAM or SRAM (static RA
M) such as a memory circuit, a microprocessor having a CMOS structure, or various CMOs such as a CMOS gate array
It can be widely used for S semiconductor integrated circuit devices that can be operated by a relatively low voltage.

[0052]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the N-channel MOSFET connected in series between the power supply voltage which is a relatively low voltage and the ground potential of the circuit is complementarily switch-controlled to obtain an output signal from the external terminal, and the power supply voltage side Drive poem supplied to the gate of the output MOSFET Q1 of
An output MOSFET that forms an output level on the power supply voltage side by using an N-channel MOSFET to achieve high integration and speed while forming the output voltage by using a MOS circuit and boosting its operating voltage using a bootstrap circuit. Since the gate voltage of can be set to a high voltage corresponding to the boosted voltage, the output level can be set to a level corresponding to the power supply voltage.

As a booster circuit, a signal to be output is supplied to one electrode via an inverter circuit, and the other electrode of a capacitor is charged up via a diode type N-channel first MOSFET. , The second capacitor is charged up in response to the signal to be output via the MOSFET controlled by the boosted voltage formed by the first capacitor, and the boosted voltage formed by the second capacitor is charged by the second capacitor. C
By forming the operating voltage of the MOS drive circuit, the boosted voltage can be formed when necessary according to the signal to be output, without providing a special timing pulse or control signal.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing an embodiment of an output circuit according to the present invention.

FIG. 2 is a specific circuit diagram showing an embodiment of an output circuit according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a synchronous non-volatile DRAM to which the present invention is applied.

[Explanation of symbols]

Q1-Q7 ... MOSFET, IV, IV1-IV3 ... C
MOS inverter circuit, C1, C2 ... Capacitor, 22
... SDRAM, 30 ... Mode register, 200A, 20
0B ... Memory array, 201A, 201B ... Row decoder, 202A, 202B ... Sense amplifier and column selection circuit, 203A, 203B ... Column decoder, 205 ...
Column address buffer, 206 ... Row address buffer, 207 ... Column address counter, 208 ... Refresh counter, 210 ... Input buffer, 211 ... Output buffer, 212 ... Controller.

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/092 9055-4M H01L 27/08 321 L

Claims (3)

[Claims] 1. An N-channel MOSFET which is connected in series between a power supply voltage, which is set to a relatively low voltage, and the ground potential of the circuit, and the connection point of which is connected to an external terminal.
An output circuit composed of Q1 and Q2, a CMOS drive circuit that forms a drive line supplied to the gate of the output MOSFET Q1 on the power supply voltage side, and a booster circuit that forms an operating voltage of the CMOS drive circuit using a bootstrap circuit. A semiconductor integrated circuit device comprising: 2. The booster circuit is such that a signal to be output is supplied to one electrode via an inverter circuit, and the other electrode is a diode type N-channel type first MO transistor.
A diode-type N provided between a first capacitor to which a power supply voltage is applied via an SFET and the other electrode of the first capacitor and the power supply voltage to clamp a boosted voltage by the first capacitor. A channel-type second MOSFET, an N-channel type third MOSFET whose gate is connected to the other electrode of the first capacitor, and which supplies a power supply voltage to the CMOS drive circuit;
The signal to be output is supplied to one electrode and the other electrode is composed of a second capacitor connected to the operating voltage terminal of the CMOS drive circuit, and the signal to be output is output via an inverter circuit. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is supplied to a CMOS drive circuit. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the power supply voltage set to the relatively low voltage is a low voltage of about 3 V or less.