JPH11273346A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an initial transient response operation to be performed at a high speed in an overdrive-type sense amplifier. SOLUTION: When a sense amplifier SA is activated, an external power source voltage VCC is supplied as an operating power source of the sense amplifier SA. This operating power source is then switched to a dropped voltage VDLP having a level lower than the external power source voltage. In an overdrive technique, each of high levels for turning on a MOS transistor M3 which supplies a ground voltage to a lower potential side drive line CSN of the sense amplifier SA and a MOS transistor M2 which supplies the dropped voltage to a higher potential side drive line CSP of the sense amplifier SA is set as a boosted voltage VPP having a level higher than the dropped voltage. Even when an operating voltage is reduced in accordance with finer processing and higher-order integration of a device, the operation at a high speed of a sense amplifier SA incorporated in such a circuit section that is to be driven with a low voltage is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a differential amplifier circuit driven in an overdrive mode, and more particularly to a DRAM (Dynamic Random Access Memory) having a low operating voltage for high integration. The present invention relates to a technology effective when applied to an access memory) or an SDRAM (synchronous dynamic random access memory).

[0002]

2. Description of the Related Art In order to increase the storage capacity of a memory, a MOS transistor such as a memory cell transistor (hereinafter referred to as M
OSFETs) have been miniaturized, thereby reducing M
Since the gate oxide film becomes thinner as the gate length of the OS transistor is reduced, the operating voltage is being reduced. In particular, DRAMs and SDRAMs attempt to perform high-level writing (charging operation on the storage capacity of memory cells) without lowering the high-level reading operation efficiency (or relatively increasing the high-level reading operation margin). In this case, it is effective to increase the selection level of the word line or lower the voltage of the data line to which the data input / output terminal of the memory cell is coupled (the level reached by the amplification operation of the sense amplifier). However, as described above, with the high integration of transistors, MO
When the gate oxide film of the S transistor is thin, if the voltage level of the word line is raised unnecessarily, the gate oxide film is easily broken, which is not preferable in terms of reliability. Under such circumstances, it is necessary to lower the voltage of the data line. Such a reduction in the voltage of the data line hinders the high-speed operation of the sense amplifier. That is, when the voltage of the operating power supply of the sense amplifier is reduced, the current flowing through the sense amplifier decreases, and when the charge information of the memory cell is read out to the data line, the minute potential difference formed on the complementary data line is reduced. The speed of amplification is reduced.

[0003] As a technique for operating a sense amplifier at high speed under a low voltage, there is an overdrive technique for the sense amplifier. For example, when the sense amplifier is configured in a CMOS static latch form, an external power supply voltage is applied to the source of the p-channel MOS transistor at the beginning of the sense amplifier activation timing, and then a voltage obtained by reducing the external power supply voltage is applied to the source of the p-channel MOS transistor. Operate the sense amplifier. This speeds up the initial transient response operation in the amplification operation of the sense amplifier.

[0004] One of the sense amplifier overdrive techniques is ISSCC95A 29ns64MbDRAM with Hiera.
Reported in chical Arry Architecture / FA14.2.

[0005]

However, the above-mentioned overdrive type sense amplifier is designed to supply operation power to the high-potential side drive line of the sense amplifier in order to speed up the operation. No consideration is given to speeding up the supply of operating power to the side drive lines.

An object of the present invention is to provide a semiconductor device capable of realizing a high-speed initial transient response operation in an overdrive type sense amplifier.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

In order to ensure a high-speed operation of a sense amplifier (SA) included in a circuit portion driven at a low voltage when the operating voltage is reduced due to miniaturization or high integration of the element, the sense amplifier is activated. At the timing, first, the external power supply voltage (V
CC) and then switching the operation power supply to a step-down voltage (VDLP) having a lower level than the external power supply voltage.
In this case, the power switch MOS transistor (M3) for supplying the ground voltage (GND) to the low potential side drive line (CSN) of the sense amplifier and the step-down voltage to the high potential side drive line (CSP) of the sense amplifier (VDLP) to turn on the power switch MOS transistor (M2) for supplying the high level.
In both cases, a boosted voltage (VP) which is higher than the step-down voltage by the threshold voltage of the power switch MOS transistor or more.
P).

According to the above means, at the beginning of the activation of the sense amplifier, the high-potential side drive line is supplied with the boosted voltage having a higher level than the step-down voltage which is the high level at which the output of the sense amplifier is attained. The gate voltage of the transistor for supplying the ground voltage to the low potential side drive line is also set to the boosted voltage, whereby the transient response operation of the sense amplifier is sped up, which contributes to the speeding up of the data read operation.

In a more detailed aspect of the present invention, a semiconductor device includes a step-down circuit for stepping down an external power supply voltage, a sense amplifier for amplifying a potential difference of a complementary bit line connected to a data input / output terminal of a dynamic memory cell, A p-channel first MOS transistor for supplying an external power supply voltage to a high-potential side drive line of the sense amplifier, an n-channel second MOS transistor for supplying the step-down voltage to a previous high-potential side drive line, and the sense amplifier An n-channel type third MOS transistor for supplying a ground voltage to the low-potential side drive line;
A control circuit for generating a switch control signal for the MOS transistor. The control circuit, when a ground voltage is supplied from the third MOS transistor to the low potential side drive line to activate the sense amplifier, supply of operating power to a high potential side drive line by the first MOS transistor. Controlling the switching from the supply of the external power supply voltage to the supply of the step-down voltage by the second MOS transistor, wherein the switching control signal of the first MOS transistor has a high level substantially equal to the external power supply voltage; And the switching control signal of the third MOS transistor is higher than the step-down voltage by the second control signal.
It has a high level substantially equal to the boosted voltage boosted above the threshold voltage of the MOS transistor.

Even if the operating voltage of the sense amplifier is reduced, if the MOS transistor for supplying the operating power to the high-potential side drive line is an n-channel type, a gate-source voltage for turning it on is used. Is the MO
It can be determined according to factors such as the breakdown voltage of the gate oxide film of the S transistor. Therefore, there is no tendency that the gate-source voltage decreases as the operating voltage of the sense amplifier decreases. Also, the carrier mobility is n compared to a p-channel MOS transistor.
Since the channel type MOS transistor is about three times as large, a relatively large current supply capability can be obtained even with a gate-source voltage equal to or lower than that of the p-channel type MOS transistor. Can be. As a result, as the operating voltage becomes lower, the operating power supply MO
It is possible to avoid a reduction in the gate-source voltage of the S transistor, and to operate the differential amplifier circuit at high speed even in a situation where the operating voltage is reduced.

By using, as the boosted voltage, the output of a booster circuit that forms a word line selection level, an increase in the circuit scale can be minimized when the operation speed of the sense amplifier is increased.

[0014]

FIG. 3 is a block diagram of an SDRAM which is an example of a semiconductor device according to the present invention. Although not particularly limited, the SDRAM 1 shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. This SDRAM 1
Are the memory array 10A and the bank B
Is provided. Each of the memory arrays 10A and 10B includes dynamic memory cells MC arranged in a matrix. According to the drawing, the selection terminals of the memory cells MC arranged in the same column are coupled to the word line WL for each column. The data input / output terminals of the memory cells arranged on the same row are coupled to complementary data lines BL, BLb for each row. Although only a part of the word lines and the complementary data lines are representatively shown in FIG. 1, a large number are actually arranged in a matrix.

One of the word lines WL of the memory array 10A selected according to the decoding result of the row address signal by the row decoder 11A is driven to a selected level by the word driver 12A.

The complementary data lines of the memory array 10A are connected to a sense amplifier and column selection circuit 13A. The sense amplifier in the sense amplifier and column selection circuit 13A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell MC. The column switch circuit in that,
This is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data line. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 15A. Similarly, on the memory array 200B side, the row decoder 11B, the word driver 12B, the sense amplifier and the column selection circuit 13B,
Further, a column decoder 15B is provided. The complementary common data line 14 is connected to an output terminal of a data input buffer 16 and an input terminal of a data output buffer 17. The input terminal of the data input buffer 16 and the output terminal of the data output buffer 17 are connected to 16-bit data input / output terminals I / O0 to I / O15.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 20 and the row address buffer 21 in an address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 21 takes in a refresh address signal output from the refresh counter 22 as a row address signal. The output of the column address buffer 20 is supplied as preset data of a column address counter 23. The column address counter 23 outputs a column address signal as the preset data or its column address in accordance with an operation mode specified by a command described later. The value obtained by sequentially incrementing the signal is output to the column decoders 15A and 15B.

The controller 25 includes, but is not limited to, a clock signal CLK, a clock enable signal CKE, and a chip select signal CSb as external control signals.
(The suffix b means that the signal to which it is attached is a row enable signal), the column address strobe signal CASb, and the row address strobe signal RA.
Sb, a write enable signal WEb, and data enable signals DQKL and DQMU are input. Furthermore,
Control data is supplied to the controller 25 from address input terminals A0 to A9 via a signal path (not shown). The controller 25 forms an internal timing signal for controlling the operation mode of the SDRAM and the operation of the above-described circuit block based on the level of the signal and the timing of the change, and the like, and a control logic (not shown) for that. A mode register 26 is provided.

The clock signal CLK is used as a master clock of the SDRAM 1, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

The chip select signal CSb indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

Each of the signals RASb, CASb, and WEb has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. In the case of the power down mode, the clock enable signal CKE is at a low level.

The data enable signals DQML, DQ
The MU controls output enable for the data output buffer 211 in, for example, the read mode. When the signals DQML and DQMU are at a high level,
The data output buffer 211 brings all of the terminals I / O0 to I / O15 into a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK.

The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at the low level, the memory bank A is selected, and when it is at the high level, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the non-selected memory bank are not selected, the data input buffer 16 and the data of only the selected memory bank are selected. This can be performed by processing such as connection to the output buffer 17.

A in the precharge command cycle
The input of 8 indicates a mode of a precharge operation for a complementary data line or the like, a high level thereof indicates that both memory banks are to be precharged, and a low level thereof indicates a state indicated by A9. Indicates that the memory bank is to be precharged.

The column address signal is A0 in a read or write command (column address / read command, column address / write command described later) cycle synchronized with the rising edge of the clock signal CLK.
ＡA7. The column address defined in this way is used as a start address for burst access.

Next, commands of the SDRAM 1 will be briefly described. [1] The mode register set command is a command for setting the mode register 26. This command is used for CSb, RASb, CASb, W
The command is specified by Eb = low level, and the data to be set (register set data) are A0 to A
9 (A0 to A9 are provided by the controller 21).
2 is omitted from the drawing). Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like.
[2] The row address strobe / bank active command is a command for validating a row address strobe instruction and selecting a memory bank by A9.
Instructed by RASb = low level and CASb, WEb = high level. At this time, the address supplied to A0 to A8 is captured as a row address signal, and the signal supplied to A9 is captured as a memory bank selection signal. The fetch operation is performed in synchronization with the rising edge of the clock signal CLK as described above. [3] The column address read command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe.
ASb, = Low level, RASb, WEb = High level, and at this time, the addresses supplied to A0 to A7 are captured as column address signals. The fetched column address signal is supplied to the column address counter 23 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. Are sequentially selected in accordance with the address signal output from the column address counter 23, and data is continuously read. The number of data to be continuously read is the number specified by the burst length. Further, the start of reading data from the data output buffer 17 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency. In addition, there are a column address / write command, a precharge command, an auto refresh command, and the like, but the description thereof is omitted here.

The SDRAM shown in FIG. 3 receives external power supply voltage VCC such as 3.3 V from an external power supply terminal. However, in order to increase storage capacity, memory arrays 10A and 10B are used.
The MOS transistors in the memory arrays 10A and 10B are reduced in size because the gate oxide film is thinned with the reduction in the gate length of the MOS transistors. . 2 V as a basic operation power supply. Step-down voltage VDLP is formed by stepping down external power supply voltage VCC by step-down circuit 30. Further, in order to increase the amount of charge signals read from the memory cells, the word line selection level is set to the boosted voltage VPP. Step-up voltage VPP
Although not particularly limited, is formed by boosting the step-down voltage VDLP by the booster circuit 31.

FIG. 1 shows a circuit for supplying operating power to the sense amplifier. The overdrive control of the sense amplifier will be described with reference to FIG.

In the figure, SA is a sense amplifier,
1 with one input terminal coupled to the other output terminal
It is configured in a static latch form by a pair of CMOS inverters. M1 in the sense amplifier SA
0 is a p-channel MOS transistor, and M11 is an n-channel MOS transistor. CSP is a high potential side drive line of the sense amplifier SA, and CSN is a low potential side drive line of the sense amplifier SA. The drive lines CSN and CSP are shared by many sense amplifiers SA for each memory mat.

In FIG. 1, M1 is a p-channel first MOS transistor for supplying an external power supply voltage VCC to the high potential side drive line CSP, and M2 is an n-channel type MOS transistor for supplying a step-down voltage VDLP to the high potential side drive line CSP. The second MOS transistor M3 is connected to the ground potential GN to the low potential side drive line CSN of the sense amplifier SA
An n-channel third MOS transistor for supplying D. The gate control signal SAP1 of the MOS transistor M1 is output from an inverter 41 using an external power supply voltage VCC as an operating power supply, and the gate control signal SAP2 of the MOS transistor M2 is output from an inverter 42 using an boosted voltage VPP as an operating power supply. The gate control signal SAN of the MOS transistor M3 is output from the inverter 43 using the boosted voltage VPP as an operation power supply. The input signals of the inverters 41 to 43 are output from the controller 25.

M4 and M5 are a pair of complementary data lines BL
A column switch for selectively conducting T and BLB to the complementary common data line 14, and a corresponding column selection signal Y
The switch is controlled by S.

As described above, the SDRAM 1 lowers the operating power supply of the memory arrays 10A and 10B in order to miniaturize the storage element, and for example, reduces the step-down voltage VD such as 2.2V.
LP. At this time, if only the step-down voltage VDLP is supplied to the drive line CSP, the sense amplifier S
Since the operation speed of A becomes slow, the sense amplifier overdrive technology is applied, in which the external power supply voltage VCC is applied to the drive line CSP at the start of the sense amplifier activation timing, and then the step-down voltage VDLP is applied. Have been. At this time, in order to further increase the operating current of the sense amplifier SA to improve the speed, M
The gate voltage of the OS transistor M3 is set to the boost voltage VPP, and the conductance of the MOS transistor M3 is increased.

FIG. 2 shows an example of a timing waveform of the overdrive operation for the sense amplifier SA.
When the sense amplifier is to be activated by control logic (not shown) of the controller 25, first, the control signal S
AN is set to a high level (step-up level VPP) and the 3M
OS transistor M3 is turned on (at time t
1). Next, at time t2, the control signal SAP1 is changed to low level, the first MOS transistor M1 is turned on, and the power supply voltage VCC is supplied to the drive line CSP. As a result, the current flowing through the p-channel MOS transistor M10 of the sense amplifier SA is made relatively large, so that the minute potential difference appearing on the complementary data lines BLT and BLB by the memory cell selecting operation is quickly amplified. Next, at time t3, the control signal SAP1 is inverted to the high level and the control signal SAP2 is set to the high level, so that the step-down voltage VDL is supplied to the drive line CSP via the second MOS transistor M2. As a result, one of the arrival levels of the complementary data lines BLT and BLB driven by the sense amplifier SA is defined as the ground voltage GND and the other is defined as the step-down voltage VDLP.

The MOS transistor M2 is of an n-channel type, and has a control signal SA for turning it on.
The high level of P2 indicates that its drain voltage (step-down voltage VD
L), for example, a word line boosted voltage VPP
Therefore, the gate-source voltage of the MOS transistor M2 is set relatively high. The carrier mobility of the n-channel MOS transistor is about three times as large as that of the p-channel MOS transistor. Therefore, the conductance of the MOS transistor M2 can be increased as compared with the case where the transistor M2 is of a p-channel type and its gate voltage is set to the ground voltage to be turned on.

When the MOS transistor M2 is turned on at the ground voltage GND with the p-channel MOS transistor M2, the gate-source voltage is set to the step-down voltage VDL, and the lower the operating voltage of the sense amplifier SA becomes, the lower the voltage becomes. Gate·
The voltage between the sources tends to be reduced. On the other hand, as shown in FIG.
In the configuration in which is turned on by the boost voltage VPP, n
The gate-source voltage for turning on the channel type MOS transistor M2 can be determined according to factors such as the withstand voltage of the gate oxide film of the MOS transistor M2,
There is no tendency for the gate-source voltage to decrease as the operating voltage decreases.

Further, the control signal SAN of the MOS transistor M3 for driving the low potential side drive line CSN has the boosted voltage VPP as a high level. Therefore, MOS
The conductance of the transistor M3 is determined by the control signal SAN.
Is higher than that of the power supply voltage VCC. Waveform (A) of FIG. 2 shows a case where the boosted voltage VPP is at the high level, and waveform (B) shows a case where the external power supply voltage VCC is at the high level. As is clear from the figure, the high level of the MOS transistor M3 is
By using PP, the transition time to the ground voltage during the transient response period of the sense amplifier SA is also reduced.

Therefore, in a situation where the operating voltage is expected to be lowered in the future, the MOS transistor M2 of the high-potential side drive line CSP is made to be an n-channel type and is controlled to be turned on by the boosted voltage VPP. The configuration in which the n-channel type MOS transistor M3 of the low potential side drive line CSN is controlled to the ON state by the boosted voltage VPP can amplify the level of the data line to a desired level at high speed and surely. Excellent in high-speed operation.

Further, a MOS transistor M using the output VPP of the booster circuit 31 for forming a word line selection level is used.
2 by generating the switch control signal SAP2 of
When the operation speed of the sense amplifier SA is increased, the increase in the circuit scale can be suppressed as much as possible.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, the boosted voltage may be formed by boosting an external power supply voltage. In the above description, the case where the invention made by the present inventor is mainly applied to the SDRAM which is the field of application as the background has been described. However, the present invention is not limited thereto, and the DRAM, and furthermore,
The present invention can be widely applied to various semiconductor devices such as a semiconductor device for data processing such as a microprocessor or a microcomputer having an on-chip memory such as an SDRAM.

The present invention can be applied to a semiconductor device provided with a sense amplifier that is overdriven by lowering the operating voltage.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the MO of the high potential side drive line
The configuration in which the S transistor is an n-channel type and is controlled to be on by a boosted voltage, and the n-channel MOS transistor of the low potential side drive line is controlled to be on by a boosted voltage, the level of the data line is set to It is possible to amplify the signal to a desired level at high speed and reliably, and to speed up the operation of the sense amplifier.

Further, by using the boosted voltage of the booster circuit for forming the word line selection level as the boosted voltage, an increase in the circuit scale can be suppressed as much as possible when the operation speed of the sense amplifier is increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a detailed example of a circuit for supplying operating power to a sense amplifier.

FIG. 2 is a timing chart showing an example of a timing waveform of an overdrive operation for a sense amplifier.

FIG. 3 is an example of a semiconductor device according to the present invention, SDRA
It is a block diagram of M.

[Description of Signs] 1 SDRAM 10A, 10B Memory array 13A, 13B Sense amplifier and column selection circuit 25 Controller 30 Step-down circuit 31 Step-up circuit VCC External power supply voltage VDDL Step-down voltage VPP Step-up voltage GND Ground voltage SA Sense amplifier M1 First MOS transistor M2 Second MOS transistor M3 Third MOS transistor BLT, BLB Complementary data line

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Sadayuki Morita 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd. 3-1-1, Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Takahiro Sonoda 3-1-1, Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra-LSI Engineering, Inc. (72) Inventor Hirotaka Ogata 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra-LSI Engineering Co., Ltd. (72) Haruko Kawauchino 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Tokyo Kiyoshi Nagai Kodaira City Josuihon-cho, Chome No. 20 No. 1 Co., Ltd. Hitachi semiconductor business unit

Claims (4)

[Claims] 1. A semiconductor device for amplifying a potential difference given to a complementary bit line by a sense amplifier according to storage information read from a dynamic memory cell, wherein a high potential of the sense amplifier is set at an activation timing of the sense amplifier. An external power supply voltage is supplied to the side drive line as an operation power supply of the sense amplifier, and then the operation power supply
A power switch MOS transistor for supplying a ground voltage to a low potential side drive line of the sense amplifier, the power switch MOS transistor having a control circuit for performing overdrive control for switching to a step-down voltage lower in level than the external power supply voltage, The high level for turning on the power switch MOS transistor for supplying the step-down voltage to the high-potential side drive line is set to a boosted voltage that is higher than the step-down voltage by the threshold voltage of the power switch MOS transistor or more. A semiconductor device, characterized in that: 2. A step-down circuit for stepping down an external power supply voltage, a sense amplifier for amplifying a potential difference of a complementary bit line connected to a data input / output terminal of a dynamic memory cell, and a high-potential drive line of the sense amplifier. A p-channel type first MOS transistor for supplying an external power supply voltage, an n-channel type second MOS transistor for supplying the step-down voltage to the previous high potential side drive line, and a ground voltage to the low potential side drive line of the sense amplifier. An n-channel type third MOS transistor to be supplied; and a control circuit for forming a switch control signal for the first to third MOS transistors. The control circuit includes a ground voltage from the third MOS transistor to the low potential side drive line. When the sense amplifier is activated to supply the high potential side drive line. For controlling the supply of operating power to the external power supply from the supply of the external power supply voltage by the first MOS transistor to the supply of a step-down voltage by the second MOS transistor. And a switching control signal for the second and third MOS transistors having a high level substantially equal to a boosted voltage that is higher than the step-down voltage by a threshold voltage of the second MOS transistor or more. A semiconductor device characterized by the above-mentioned. 3. The semiconductor according to claim 2, wherein the boosted voltage is output from a booster circuit that forms a select level of a word line to which a select terminal of the dynamic memory cell is coupled. apparatus. 4. The semiconductor device according to claim 3, wherein said control means delays an on-operation timing of said first MOS transistor from an on-operation timing of said third MOS transistor.