JPH11273341A - Semiconductor device and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a semiconductor device which has a differential input buffer between itself and an external interface circuit. SOLUTION: The semiconductor device has a differential input buffer 1 and a latch circuit 2 having its input connected to the output of the differential input buffer. The differential input buffer 1 has a differential input amplifier which inputs a reference potential Vref and an external signal IN differentially, a power switch Q5 which supplies a high-potential side current to the differential amplifier, and a 2nd power switch Q6 which supplies a low-potential side current to the differential input amplifier. A control circuit 3 controls the differential input buffer 1 into alternate active and inactive states according to the state of a synchronizing clock signal QCLKb and also controls the latch circuit 2 into input and latch states synchronously, so a through current is prevented from always passing through the differential input buffer 1, thereby reducing the power consumption of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a differential input buffer in an external interface circuit, and more particularly to a technique for reducing the power consumption of a differential input buffer. (Random access memory).

[0002]

2. Description of the Related Art As a small signal amplitude interface for memory modules, SSTL (Stub Series Terminated t
ransceiver Logic). When a small signal amplitude interface represented by this interface specification is realized by a semiconductor device, a differential input buffer can be employed for an external interface circuit. For example, in the SSTL interface, Vref (≒ Vcc × 0.45) is used as a reference potential, a current mirror type differential amplifier is provided in the first stage of an external input of a semiconductor device, and an input signal can be input to a CMOS at a high speed.
The level is converted to a level, and the input data is latched by a latch circuit at a subsequent stage.

As an example of a document describing a semiconductor device having the SSTL interface specification, H. 8
There is an EIAJ ED-5512, 3.3V stub series terminated logic standard functional specification.

[0004]

However, in a semiconductor device in which the SSTL interface specification is adopted as the external interface specification, all of the external signal interface circuits have the current mirror type differential amplifier in the input first stage buffer. , They must always be input enabled. It has been found by the present inventor that if the operating current is continuously supplied to keep the current mirror type differential amplifier operable, the power consumption of the semiconductor device and further the entire system becomes excessively large. .

An object of the present invention is to reduce power consumption of a semiconductor device having a differential input buffer in an external interface circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A semiconductor device has a differential input buffer (1), which is an input interface circuit for external signals, and a latch circuit (2) having an input connected to the output of the differential input buffer. Operate synchronously. The differential input buffer supplies a differential input amplifier having one differential input as a reference potential (Vref) and the other differential input as an external signal (IN), and a high potential side power supply to the differential input amplifier. And a second power switch transistor (Q6) for supplying low-potential-side power to the differential input amplifier. A control circuit (3) that controls the differential input buffer and the latch circuit turns on the first and second power switch transistors in synchronization with the first state of the input operation synchronous clock signal (QCLKb). Control to activate the differential input buffer and enable the latch circuit to perform the input operation. The first circuit is synchronized with the second state of the synchronous clock signal for the input operation.
And controlling the second power switch transistor to an off state to inactivate the differential input buffer and control the latch circuit to a data latch state.

As described above, the differential input buffer can be alternately activated and deactivated in accordance with the state of the synchronous clock signal for the input operation, thereby reducing the through current flowing through the differential input buffer. it can.

Further, the differential input buffer has power switches on both the high potential side and the low potential side power supply systems, and in the activation / deactivation control of the buffer, both power switches are switched in parallel. Since the differential input buffer is activated, undesired inversion or large fluctuation of the output of the differential input buffer when the buffer is inactivated can be minimized. Therefore, it is not necessary to delay the deactivation timing of the differential input buffer with respect to the latch operation of the latch circuit, and the control of the latch timing of the latch circuit and the deactivation timing of the differential input buffer is simplified. In addition, the operation period of the differential input buffer can be shortened as much as possible, which is excellent from the viewpoint of low power consumption.

The control circuit is provided with a power down signal (P
D), and in response to the first state of the power down signal, regardless of the state of the clock signal,
Controlling the power switch transistor to an off state, forcing the output of the latch circuit to a predetermined logical value, and performing control according to the state of the clock signal in response to a second state of a power down signal. Can be.

[2] According to another aspect of the present invention, a transfer gate (4) is arranged between a differential input buffer and a latch circuit, and the transfer gate is closed in synchronization with a latch timing to provide a differential input. When the buffer is deactivated, its output is forcibly separated from the input of the latch circuit. Thus, the possibility that the latch circuit latches erroneous data when the differential input buffer is inactivated can be reliably eliminated. However, it is expected that the number of transistors will be slightly increased compared to the invention according to the first aspect.

The control circuit receives a power-down signal, controls the power switch transistor and the transfer gate to be in an OFF state in response to a first state of the power-down signal, irrespective of the state of the clock signal, and The output of the latch circuit is forced to a predetermined logical value, and control according to the state of the clock signal can be performed in response to the second state of the power down signal.

By providing a precharge transistor (Q9) for precharging between the output terminal of the differential input buffer and the transfer gate in synchronization with the second state of the clock signal, the differential input transistor Is activated, the speed of the differential amplification operation can be guaranteed.

[3] The semiconductor device includes an address input buffer (20, 2) having the differential input buffer, respectively.
1) having a data input buffer (16) and a control signal input buffer (28), externally inputting a command in a state where a chip is selected by a chip selection signal (CSb);
It can be realized as an SDRAM (5) or the like that decodes an input command and performs a memory operation on a memory cell (MC). The data processing system can be configured by mounting such a semiconductor device and an access control circuit (111, 113) for supplying a command to the semiconductor device on a mounting board. Since a semiconductor device with lower power consumption than that described above is used, power consumption of the entire data processing system can be reduced.

[0016]

FIG. 1 shows an example of a semiconductor device according to the present invention. FIG. 1 representatively shows a circuit portion centered on one differential input buffer. The semiconductor device shown in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon by, for example, a known CMOS integrated circuit manufacturing technique, and is operated in synchronization with a clock signal.

In FIG. 1, 1 is a differential input buffer, 2
Indicates a latch circuit, and 3 indicates a control circuit. The differential input buffer 1 is an input interface circuit for external signals.
IN means an external input signal. Although not particularly limited,
The differential input buffer 1 is an SSTL interface buffer that satisfies the SSTL interface specification. FIG.
Here, the input protection circuit and the like are not shown.

The differential input buffer 1 has a differential input amplifier constituted by a pair of differential input MOS transistors Q1 and Q2 and a current mirror load by MOS transistors Q3 and Q4. Differential input transistor Q2 receives reference potential Vref, and differential input transistor Q1 receives external input signal IN at its gate. The common source of the MOS transistors Q3 and Q4 is provided with a p-channel first power switch MOS transistor Q5 for supplying the high potential power supply VCC, and the common source of the MOS transistors Q1 and Q2 is provided with a low potential power supply. G
An n-channel second power switch MOS transistor Q6 for supplying ND is provided.

The latch circuit 2 includes, but is not limited to, a NOR gate NOR2 and a clocked inverter CIV.
Are connected in anti-parallel. OUT is an output signal of the latch circuit 2.

The control circuit 3 has a NOR gate NOR1 and an inverter IV, and has a clock signal QC for input operation.
The operation of the differential input buffer 1 and the latch circuit 2 is controlled based on LKb and the power down signal PD. The NOR gate NOR1 receives the timing clock signal QCLKb and the power down signal PD. Power down signal PD
Indicates power down by a high level. The timing clock signal QCLKb is a clock signal such as a one-shot pulse which is set to a low level for a certain period every operation cycle of the semiconductor device as illustrated in FIG. The output of the NOR gate NOR1 is supplied to the gate of the MOS transistor Q6, and is also supplied to the gate of the MOS transistor Q5 via the inverter IV, whereby the power switch MOS transistors Q5 and Q6
Is turned on during a low level period of the timing clock signal QCLKb and turned off during a high level period, provided that the power down signal PD is at a low level. Further, the output of the NOR gate NOR1 and the inverter IV activates the clocked inverter CIV of the latch circuit.
Inactive control is performed, and the latch circuit 2 is enabled to input during a low level period of the timing clock signal QCLKb, and is controlled to a latch state during a high level period, on condition that the power down signal PD is at a low level. This timing is as illustrated in FIG. In FIG. 2, a clock signal CLK is an operation reference clock signal for generating the clock signal QCLKb.

When the power down signal PD is at a high level, the power switch MOS transistor Q is turned on regardless of the state of the timing clock signal QCLKb.
5, Q6 are controlled to the off state, and the output of the latch circuit 2 is forced to a low level.

According to the above configuration, the differential input buffer 1 can be alternately activated and deactivated according to the state of the input operation timing clock signal QCLKb, so that the through current consumed by the differential input buffer 1 is reduced. can do.

Further, the differential input buffer has power switch MOS transistors Q5 and Q6 in the power supply system on both the high potential side and the low potential side. Since the MOS transistors Q5 and Q6 are switched in parallel, it is possible to minimize a situation where the output of the differential input buffer 1 is undesirably inverted or fluctuated when the differential input buffer 1 is inactivated. it can. Therefore, since it is not necessary to delay the inactivation timing of the differential input buffer 1 with respect to the latch operation of the latch circuit 2, it is easy to control the latch timing of the latch circuit and the inactivation timing of the differential input buffer. In addition, the operation period of the differential input buffer can be shortened as much as possible, which is excellent from the viewpoint of low power consumption.

FIG. 3 shows another example of the semiconductor device according to the present invention. FIG. 1 representatively shows a circuit portion centered on one differential input buffer. The semiconductor device shown in FIG. 3 is formed on one semiconductor substrate such as single crystal silicon by, for example, a known CMOS integrated circuit manufacturing technique, and is operated in synchronization with a clock signal.

In FIG. 3, reference numeral 1 denotes a differential input buffer;
Indicates a latch circuit, and 3 indicates a control circuit. The differential input buffer 1 is an external signal input interface circuit. I
N means an external input signal. Although not particularly limited, the differential input buffer 1 is an SSTL interface buffer satisfying the SSTL interface specification. In FIG. 3, the input protection circuit and the like are not shown.

The difference from FIG. 1 is that the power switch MOS transistor of the differential input buffer 1 is only Q6 on the low potential side, and a p-channel type MOS transistor is provided between the differential input buffer 1 and the latch circuit 2. CM composed of transistor Q7 and n-channel MOS transistor Q8
That the OS transfer gate 4 is provided, and
That is, a p-channel type precharge MOS transistor Q9 is provided at the output terminal of the differential input buffer 1. The control circuit 3 switches and controls the power switch MOS transistor Q6 according to the output of the NOR gate NOR1. The CMOS transfer gate 4 has a NOR gate N
The switch is controlled by the output of the OR1 and the output of the inverter IV, is closed in synchronization with the latch timing by the latch circuit 2, and when the differential input buffer 1 is deactivated, its output is forcibly applied from the input of the latch circuit 2. Let it separate. As a result, the possibility that the latch circuit 2 latches erroneous data when the differential input buffer 1 is inactivated can be reliably eliminated. The precharge MOS transistor Q9 precharges the output terminal of the differential input buffer 1 toward the power supply voltage VCC at the latch timing of the latch circuit 2 (inactive period of the differential input buffer). Thereby, when the differential input buffer 1 is activated, high speed operation of the differential amplification operation can be guaranteed.

The configuration of FIG. 3 has a slightly larger number of transistors than the configuration of FIG. The power down control by the power down signal PD is the same as in FIG. The CMO
The S transfer gate 4 is cut off during power down.

FIG. 4 is a block diagram of an SDRAM which is an example of a semiconductor device according to the present invention. Although not particularly limited, the SDRAM 5 shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The input circuit using the differential input buffer 1, the latch circuit 2, the control circuit 3 and the like described in FIGS. 1 to 3 includes a column address buffer 20, a row address buffer 21, a control signal input shown in FIG. It is applied to the buffer 28 and the data input buffer 16, respectively. The timing clock signal QCLKb and the power down signal PD are output from the controller 25 in accordance with the operation of the SDRAM 5.

The SDRAM 5 shown in FIG.
And a memory array 10B forming a bank B. Each memory array 10
A and 10B include dynamic memory cells MC arranged in a matrix. According to the figure, the selection terminals of the memory cells MC arranged in the same column are coupled to the word line WL of each column and arranged in the same row. The data input / output terminals of the memory cells are connected to complementary data lines BL and BLb for each row.
Although only a part of the word lines and the complementary data lines are representatively shown in FIG. 1, a large number are actually arranged in a matrix.

One of the word lines WL of the memory array 10A selected according to the decoding result of the row address signal by the row decoder 11A is driven to a selected level by the word driver 12A.

The complementary data lines of the memory array 10A are connected to a sense amplifier and column selection circuit 13A. The sense amplifier in the sense amplifier and column selection circuit 13A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell MC. The column switch circuit in that,
This is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data line. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 15A. Similarly, a row decoder 11B, a word driver 12B, a sense amplifier and a column selection circuit 13B, and a column decoder 15B are provided on the memory array 10B side. The complementary common data line 14 is connected to an output terminal of a data input buffer 16 and an input terminal of a data output buffer 17.
The input terminal of the data input buffer 16 and the output terminal of the data output buffer 17 are 16-bit data input / output terminals I.
/ O0 to I / O15.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 20 and the row address buffer 21 in an address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 21 takes in a refresh address signal output from the refresh counter 22 as a row address signal. The output of the column address buffer 20 is supplied as preset data of a column address counter 23. The column address counter 23 outputs a column address signal as the preset data or its column address in accordance with an operation mode specified by a command described later. The value obtained by sequentially incrementing the signal is output to the column decoders 15A and 15B.

The controller 25 includes, but is not limited to, a clock signal CLK, a clock enable signal CKE, a chip select signal CSb,
Column address strobe signal CASb, row address strobe signal RASb, and write enable signal W
Eb and data enable signals DQKL and DQMU are input. Further, control data is supplied to the controller 25 from address input terminals A0 to A9 via a signal path (not shown). The controller 25 performs the SDRA based on the levels of the signals and the timing of the change.
It forms an internal timing signal for controlling the operation mode of M and the operation of the circuit block, and includes a control logic (not shown) and a mode register 26 therefor.

The clock signal CLK is used as a master clock of the SDRAM 5, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

The chip select signal CSb indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

Each of the signals RASb, CASb, and WEb has a different function from a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. In the case of the power down mode, the clock enable signal CKE is at a low level.

The data enable signals DQML, DQ
The MU controls output enable for the data output buffer 17 in, for example, the read mode.
When the signals DQML and DQMU are at a high level, the data output buffer 17 sets all of the terminals I / O0 to I / O15 to a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK.

The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at the low level, the memory bank A is selected, and when it is at the high level, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the non-selected memory bank are not selected, the data input buffer 16 and the data of only the selected memory bank are selected. This can be performed by processing such as connection to the output buffer 17.

A in the precharge command cycle
The input of 8 indicates a mode of a precharge operation for a complementary data line or the like, a high level thereof indicates that both memory banks are to be precharged, and a low level thereof indicates a state indicated by A9. Indicates that the memory bank is to be precharged.

The column address signal is A0 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK.
ＡA7. The column address defined in this way is used as a start address for burst access.

Next, commands of the SDRAM 5 will be briefly described. [1] The mode register set command is a command for setting the mode register 26. This command is used for CSb, RASb, CASb, W
The command is specified by Eb = low level, and the data to be set (register set data) are A0 to A
9 (A0 to A9 are provided by the controller 21).
2 is omitted from the drawing). Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like.
[2] The row address strobe / bank active command is a command for validating a row address strobe instruction and selecting a memory bank by A9.
Instructed by RASb = low level and CASb, WEb = high level. At this time, the address supplied to A0 to A8 is captured as a row address signal, and the signal supplied to A9 is captured as a memory bank selection signal. The fetch operation is performed in synchronization with the rising edge of the clock signal CLK as described above. [3] The column address read command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe.
ASb, = Low level, RASb, WEb = High level, and at this time, the addresses supplied to A0 to A7 are captured as column address signals. The fetched column address signal is supplied to the column address counter 23 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. Are sequentially selected in accordance with the address signal output from the column address counter 23, and data is continuously read. The number of data to be continuously read is the number specified by the burst length. Further, the start of reading data from the data output buffer 17 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency. In addition, there are a column address / write command, a precharge command, an auto refresh command, and the like, but the description thereof is omitted here.

FIG. 5 is a block diagram of a computer system which is an example of a data processing system using the SDRAM 5. This computer system includes a processor board 110 and peripheral circuits. The processor board 110 includes a microprocessor 111 and a memory controller 113 and a PCI (Peripheral Component Interconn.) Typically shown on a processor bus 112 to which the microprocessor 111 is coupled.
ect) The bus controller 114 is coupled. The SDRAM 5 as a main memory which is a work area or a primary storage area of the microprocessor 111 is connected to the memory controller 114. The PCI bus controller 114 functions as a bridge circuit that interfaces low-speed peripheral circuits to the processor bus 112 via the PCI bus 116. The PCI bus 116 includes, but is not limited to, a display controller 117,
IDE (Integrated Device Electronics) interface controller 118, SCSI (Small Computer S)
ystem Interface) interface controller 119
And other interface controllers 120. The display controller 117 is connected to a frame buffer memory 121.

As a peripheral circuit, a display 122 coupled to the display controller 117 and an IDE
A hard disk drive (HDD) 123 coupled to an interface controller 118, an image scanner 124 coupled to a SCSI interface controller 119, and a keyboard 125 and a mouse 1 coupled to the other interface controllers 120
26, a modem 127, and the like.

According to the processor board 100 of FIG.
Since the SDRAM 5 with lower power consumption is used, the power consumption of the entire processor board 100 can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the configuration of the differential input amplifier is not limited to FIGS. 1 and 3, and can be changed as appropriate. Further, the semiconductor device according to the present invention is not limited to an SDRAM,
(Synchronous static random access
Memory) and other types of storage, such as SDRAM
The present invention can be widely applied to various semiconductor devices such as a semiconductor device for data processing such as a microprocessor or a microcomputer having a memory such as an on-chip memory.

The present invention can be applied to a semiconductor device under the condition that a differential input buffer is provided in an external interface circuit.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the differential input buffer is alternately activated / deactivated according to the state of the synchronous clock signal for the input operation, and the latch circuit is controlled to be in the input enabled / latch state in synchronization therewith. Accordingly, it is possible to prevent the through current from flowing constantly in the differential input buffer for the input interface of the external signal, and to contribute to low power consumption of the semiconductor device.

Power switches are provided in the power supply systems on both the high potential side and the low potential side of the differential input buffer, and the activation / inactivation of the buffer is controlled by operating both power switches in parallel. In addition, when the differential input buffer is inactivated, the output of the buffer can be prevented from being undesirably inverted or greatly fluctuated. It is not necessary to delay the activation timing, and the control of the latch timing of the latch circuit and the deactivation timing of the differential input buffer can be simplified.

A transfer gate is arranged between the differential input buffer and the latch circuit, the transfer gate is closed in synchronization with the latch timing, and when the differential input buffer is deactivated, its output is forcibly applied to the latch circuit. By separating the input from the input, it is possible to reliably eliminate the possibility that the latch circuit latches erroneous data when the differential input buffer is inactivated.

A data processing system using such a semiconductor device can reduce power consumption as a whole system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram mainly illustrating an input buffer of a semiconductor device according to the present invention.

FIG. 2 is a timing chart showing an example of an input operation waveform using a differential input buffer.

FIG. 3 is a circuit diagram showing another example mainly including an input buffer of the semiconductor device according to the present invention.

FIG. 4 is an example of a semiconductor device according to the present invention, SDRA
It is a block diagram of M.

FIG. 5 is a block diagram illustrating an example of a processor board using an SDRAM.

[Explanation of symbols]

Reference Signs List 1 Differential input buffer (SSTL interface buffer) 2 Latch circuit 3 Control circuit QCKLb Timing clock signal PD Power down signal IN External input signal Q5, Q6 Power switch MOS transistor Vref Reference potential 4 Transfer gate 5 SDRAM Q9 Precharge MOS transistor 10A, 10B Memory array 13A, 13B Sense amplifier and column selection circuit 16 Data input buffer 20 Column address buffer 21 Row address buffer 25 Controller 28 Control signal input buffer 111 Microprocessor 113 Memory controller

Continued on the front page (72) Inventor Sadayuki Morita 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Within Hitachi Ultra-SII Engineering Co., Ltd. Address 1 within Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Takanori Miyase 3-1-1 Higashi Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra LSI Engineering Co., Ltd. (72) Inventor Takahiro Sonoda 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside Hitachi ULS Engineering Co., Ltd. (72) Haruko Kawauchi 3-1-1 1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi UL (72) Inventor Kiyoshi Nagai 5-20-1, Josuihoncho, Kodaira-shi, Tokyo In-house Semiconductor Division, Hitachi, Ltd.

Claims (7)

[Claims] 1. A clock synchronous semiconductor device comprising: a differential input buffer as an input interface circuit for an external signal; and a latch circuit having an input connected to an output of the differential input buffer. An input buffer, a differential input amplifier having one differential input as a reference potential and the other differential input as an external signal;
A first power switch transistor for supplying a high-potential-side power supply to the differential input amplifier, and a second power-switch transistor for supplying a low-potential-side power supply to the differential input amplifier; The first and second power switch transistors are turned on in synchronization with a first state of a signal to activate a differential input buffer and to enable the latch circuit to perform an input operation, thereby enabling synchronization of the input operation. A control circuit for controlling the first and second power switch transistors to an off state in synchronism with a second state of a clock signal to deactivate a differential input buffer and to control the latch circuit to a data latch state. A semiconductor device comprising: 2. The control circuit receives a power-down signal and responds to a first state of the power-down signal to turn off the first and second power switch transistors regardless of the state of the clock signal. And forcing the output of the latch circuit to a predetermined logical value, and performing control according to the state of the clock signal in response to a second state of the power down signal. The semiconductor device according to claim 1. 3. A clock synchronous semiconductor device comprising: a differential input buffer as an input interface circuit for an external signal; and a latch circuit having an input connected to an output of the differential input buffer. An input buffer, a differential input amplifier having one differential input as a reference potential and the other differential input as an external signal;
A power switch transistor for supplying power to the differential input amplifier; a transfer gate disposed between an input terminal of the latch circuit and an output terminal of the differential input buffer; and a synchronous clock signal for input operation. Activating the differential input buffer by turning on the power switch transistor in synchronism with the first state, turning on the transfer gate, turning on the transfer circuit, enabling the latch circuit to perform an input operation, and synchronizing the input operation. Control for controlling the power switch transistor to an off state in synchronism with a second state of the clock signal to inactivate a differential input buffer, and to set the transfer gate to an off state and control the latch circuit to a data latch state; And a circuit. 4. The control circuit receives a power down signal and controls the power switch transistor and the transfer gate to be in an off state in response to a first state of the power down signal, regardless of a state of the clock signal. 4. The control circuit according to claim 3, wherein an output of said latch circuit is forced to a predetermined logic value, and control is performed according to a state of said clock signal in response to a second state of a power down signal. 13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, further comprising a precharge transistor that precharges between an output terminal of the differential input buffer and the transfer gate in synchronization with a second state of the clock signal. The semiconductor device according to claim 4, wherein 6. An address input buffer, a data input buffer, and a control signal input buffer each having the differential input buffer, and a command is input from the outside in a state where a chip is selected by a chip selection signal, and the input command is input. 6. The method according to claim 1, wherein the decoding is performed to perform a memory operation on a memory cell.
13. The semiconductor device according to claim 1. 7. A data processing system comprising a semiconductor device according to claim 6, and an access control circuit for supplying a command to the semiconductor device mounted on a mounting board.