JPH0887883A - Synchronous semiconductor memory - Google Patents

Abstract

PURPOSE: To decrease the number of signals required for controlling an SDRAM chip at the time of burn-in. CONSTITUTION: A burn-in mode detection circuit 30 detects the difference between power supply voltages Vcc and Vss to output a signal ϕBI representative of burn-in mode. A control signal buffer command decoder 11a outputs a signal ϕACT activated by the signal ϕBI. A memory array control circuit 12 enters into auto-refresh mode based on the signals ϕACT and ϕBI. Switches 19, 20 are turned ON and an address signal is delivered from a refresh address counter 15 to an internal circuit. Consequently, auto-refresh can be started by simply feeding a clock CLK externally and burn-in can be carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device, and more particularly to burn-in in a synchronous DRAM.

[0002]

2. Description of the Related Art In recent years, various memory LSs have been used in order to eliminate an access gap between a microprocessor and a memory.
Although I has been proposed, all of them are characterized in that input / output is performed in synchronization with an external clock to increase the data transfer rate. One of these synchronous memories is called a synchronous DRAM (hereinafter referred to as SDRAM).

FIG. 6 is a plan view of a packaged SDRAM chip for explaining control signals and the like for controlling the SDRAM. In the figure, 1 is a packaged SDRAM chip, P1 is a power supply terminal to which a power supply voltage V _CC is supplied, P2 is a power supply terminal to which a power supply voltage V _SS (0 V) is supplied, and P3 is a chip for selecting a chip. A terminal to which the select signal bar CS is supplied, P4 is a row address strobe signal bar RA for fetching a row address.
A terminal to which S is supplied, P5 is a column address strobe signal bar CAS, P6 for fetching a column address.
Is a terminal to which the write enable signal bar WE for controlling writing is supplied, P7 is a terminal to which the external clock CLK is supplied, P8 is a terminal to which the clock enable signal CKE is supplied, and P9 is a bank address for switching banks. Terminals to which the signal BA is supplied, P10 to P20 are terminals to which the address signals A0 to A10 are supplied, P21 to P2
Reference numeral 8 is an input / output terminal for the data DQ0 to DQ7, P29 is a terminal to which the output disable / write mask signal DQM is supplied, and the SDRAM chip 1 has 44 terminals including other terminals.

The SDRAM chip 1 operates in synchronization with a high-speed external clock CLK of about 100 MHz and takes in an external signal at the rising edge of the clock. And
Mainly, the high level (H) and low level (L) of the row address strobe signal bar RAS, the column address strobe signal bar CAS, and the write enable signal bar WE.
The operation command of the SDRAM chip 1 is defined by the combination with.

An example of the definition table of the SDRAM chip 1 is shown in Table 1.
Shown in For example, the row address strobe signal bar RA
S is low level, column address strobe signal bar C
If the AS and the write enable signal bar WE are at high level, the row address is taken in and the bank is activated (the word line is raised to operate the sense amplifier). If the row address strobe signal bar RAS and the write enable signal bar WE are at the high level and the column address strobe signal bar CAS is at the low level, the column address is fetched and the read operation is performed.

[0006]

[Table 1]

7 and 8 are block diagrams showing the structure of a conventional SDRAM. In FIG. 7, 10 is a CLK buffer for buffering an externally supplied clock CLK to supply an internal clock intCLK, and 11 is a combination of control signals such as a chip select signal bar CS and a row address strobe signal bar RAS. Inside
Control signal buffer command decoder for outputting signals such as NORM, φREF, and φACT, 12 is a signal φ
A memory array control circuit for controlling the memory array at the time of bank activation or refreshing in response to REF and the signal φACT, and 13 buffers address signals A0 to A10 inputted from the outside and outputs the address signals in synchronization with the internal clock. An address buffer for outputting, 14 a BA buffer for buffering an externally input bank address signal BA and outputting a bank address signal in synchronization with an internal clock, 15 a refresh address counter for outputting an address signal at the time of refresh, 16 is a self refresh control signal φ during self refresh
Self-refresh timer for outputting SR, and 17 for control signal buffer command decoder 1 during normal operation
A switch for controlling the internal supply of the address signal output from the address buffer 13 which is controlled by the signal φNORM output from 1 and 18 is a signal φN
A switch for controlling ON / OFF of the internal supply of the bank address signal BA output from the BA buffer 14 controlled by the ORM, and 19 for controlling ON / OFF by the signal φREF output from the control signal buffer command decoder 11 at the time of refreshing. A switch for controlling ON / OFF of the supply of the address signal output from the refresh address counter 15, 20 is a signal φR
The switch controls ON / OFF of the supply of the bank address signal BA output from the refresh address counter 15 and controlled by EF.

In FIG. 8, 21 is a memory array of bank 0, 22 is an memory array 21 which receives an internal address signal intXAD and an internal bank address signal intBA.
Row decoder of bank 0 for selecting the row, 23 is a column decoder of bank 0 for selecting the column of the memory array 21 by receiving the internal address signal intYAD and the internal bank address signal intBA, and 24 is a sense amplifier of the memory array 21. Is connected to the preamplifier and write buffer for reading / writing data, and 25 is an internal clock int for data DQ for writing and reading.
DQ buffer for buffering in synchronization with CLK; 26, memory array of bank 1; 27, internal address signal int
A row decoder of bank 1 which receives the XAD and the internal bank address signal intBA to select a row of the memory array 26, and 28 receives the internal address signal intYAD and the internal bank address signal intBA.
The column decoder of the bank 1 for selecting the column of, and 29 are preamplifiers and write buffers connected to the sense amplifiers of the memory array 26 for reading / writing data.

FIG. 9 shows the lead / read of a conventional SDRAM chip.
FIG. 6 is a timing diagram showing a write operation. At time t1, when the chip enable signal bar CS and the row address strobe signal bar RAS become low level and the column address strobe signal bar CAS and the write enable signal bar WE become high level, the bank 0 is activated and the row address X is captured.

At time t2, when the chip enable signal bar CS, the column address strobe signal bar CAS and the write enable signal bar WE are at the low level and the row address strobe signal bar RAS is at the high level, the 4-bit data D0 to D3. Is written in the memory array 21 at the subsequent rising edge of the clock CLK.

At time t3, the chip select signal bar CS and the column address strobe signal bar CAS are at low level, and the row address strobe signal bar R is at the low level.
When the column address Y and the bank address 0 are input when the AS and the write enable signal bar WE become high level, the 4-bit data Q0 to Q3 is read out after 3 clocks.

At time t4, the chip select signal bar CS, the row address strobe signal bar RAS and the write enable signal bar WE are at the low level, the column strobe signal bar CAS is at the high level, and the bank 0 is precharged. .

The SDRAM is provided with auto refresh and self refresh as refresh modes. FIG. 10 is a timing diagram showing the auto refresh operation of the SDRAM chip.

At time t5, the row address strobe signal bar RAS and the column address strobe signal bar CAS are at low level, and the write enable signal bar WE.
If the clock enable signal CKE is at high level, auto refresh is activated. At time t6,
When a signal similar to that at time t5 is input, the auto refresh is repeated again.

In the auto-refresh, a refresh address is generated by the internal refresh counter 16, a word line is activated, a sense amplifier is activated, and then a precharge state is automatically established. In other words, by entering the auto refresh command only once, one row of memory cells is automatically refreshed within about 100 ns. In order to refresh all the memory cells, it is usually necessary to repeat the auto refresh 4096 times.

FIG. 11 is a timing diagram showing the self-refresh operation of the SDRAM chip. At time t7, the row address strobe signal bar RAS, the column address strobe signal bar CAS, and the clock enable signal CKE become low level, and the write enable signal bar WE becomes high level, and then the clock enable signal CKE becomes low level. Self-refresh is activated.

The self-refresh is an operation in which an internal timer automatically performs the same operation as the above-described auto-refresh at regular intervals.

Not only SDRAM but also DRAM is subjected to an accelerated test called burn-in to remove structurally defective products before shipping. This is because there is a defective portion in the oxide film of the memory cell, which operates normally immediately after production, but the defective portion deteriorates with time and eventually the oxide film is destroyed. By applying 6V to the element used at 3.3V, stress is applied to detect the defective chip in a short time.

When performing SDRAM burn-in, if a high-performance tester having an operating frequency of 100 MHz is used, the write / read operation can be performed as in a normal test, but burn-in takes a long time. Since it takes (for example, 24 hours), it is usual to apply a large amount of stress (for example, in units of 100 pieces) at the same time to shorten the time. Therefore, the driver waveform of the tester is blunted by a large load capacitance, and high-speed operation cannot be performed. For example, if only 10 MHz operation is possible, at least 600 ns is required to write / read 1 bit as shown in FIG. 12 (100
In case of MHz, it becomes 200 ns), and the time required for burn-in becomes long.

In case of standard DRAM burn-in, FIG.
A row address strobe signal bar RAS and a column address strobe signal bar C for controlling the operation as shown in FIG.
Even if the operating frequency of AS is about 10 MHz, it does not cause a problem. Since the SDRAM operates in synchronization with the clock, at least three times the clock cycle is required for each memory cycle, whereas the standard DRAM requires one cycle for the row address strobe signal bar RAS and one memory cycle. Because it is completed.

[0021]

Since the conventional synchronous semiconductor memory device is constructed as described above, the standard DRA
In the test of M, it is enough to give the three signals of the row address strobe signal bar RAS, the column address strobe signal bar CAS and the write enable signal bar WE in addition to the address, whereas it is necessary to test the SDRAM. In addition to these, signals such as a clock CLK, a clock enable signal CKE, a chip select signal bar CS and an output disable / write mask signal DQM are required, and it is necessary to use an expensive high-performance type as a burn-in tester. There was a problem that it would become.

The present invention has been made to solve the above problems, and an object thereof is to reduce the number of signals required for burn-in and perform burn-in with a simple tester as in the past.

[0023]

A synchronous semiconductor memory device according to a first aspect of the present invention is a synchronous semiconductor memory device having an auto-refresh function, which is externally input when a power supply voltage is higher than a predetermined value. Regardless of the control signal
The feature is that automatic refresh is automatically started in synchronization with an external clock.

A synchronous semiconductor memory device according to a second aspect of the present invention is a synchronous semiconductor memory device having a self-refresh function, wherein a control signal and a clock input from the outside when a power supply voltage is higher than a predetermined value. The feature is that the self-refresh is automatically started regardless of the setting.

[0025]

The synchronous semiconductor memory device according to the first invention is
By supplying a power supply voltage higher than a predetermined value during the burn-in to activate the auto-refresh, the burn-in can be executed without giving an external control signal other than the external clock.

In the synchronous semiconductor memory device according to the second aspect of the present invention, a self-refresh is activated by applying a power supply voltage higher than a predetermined value at the time of burn-in, so that the burn-in can be performed without applying an external clock and an external control signal. Can be executed.

[0027]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a simplified block diagram of a control unit of an SDRAM chip according to a first embodiment of the present invention. In FIG. 1, reference numeral 30 denotes a burn-in mode detection circuit for detecting that the burn-in mode has been entered according to the value of the power supply voltage V _CC and outputting a signal φBI to an internal circuit. This is a control signal buffer command decoder which receives the signal φBI in addition to the control signal such as the address strobe signal bar RAS and outputs the signal φACT even in the burn-in mode. The other parts having the same reference numerals as those in FIG. 6 are those shown in FIG. Is a part corresponding to.

During normal bank activation (when row address strobe signal bar RAS is at low level and column address strobe signal bar CAS and write enable signal bar WE are at high level), φNORM is activated by the command decoder and the switch is activated. The external addresses A0 to A10 and the external bank address BA are transmitted by 17 and 18 to an internal circuit such as a decoder.

At the time of auto-refresh (when the row address strobe signal bar RAS and the column address strobe signal bar CAS are at the low level and the write enable signal bar WE is at the high level), φREF is activated by the command decoder and φNORM is not turned on. Becoming active,
The outputs from the internal refresh address counter 15 are transmitted to the internal circuit by the switches 19 and 20.

During the burn-in, when the power supply voltage V _CC is sufficiently higher than the normal standard (for example, 3.0-3.6 V) (for example, 5.0 V or more), the burn-in detection circuit 30 outputs the signal φ.
BI is activated and acts on the control signal buffer command decoder 11a to cause row address strobe signal bar RAS and column address strobe signal bar CA.
The output from the internal refresh address counter 15 is transmitted to the internal circuit through the switches 19 and 20 regardless of the level of the external input such as S and the write enable signal bar WE.

FIG. 2 is a circuit diagram showing the structure of the burn-in mode detection circuit. In FIG. 2, 50 is the power supply voltage V
A power supply potential point to which _CC is applied, 51 is a ground potential point to which a power supply voltage V _SS is applied, R1 is a high resistance having one end connected to the power supply potential point 50 and the other end connected to the node N1,
Q1 is an N-channel MOS transistor whose gate and drain are connected to the node N1, and Q2 is an N-channel MOS transistor whose gate and drain are connected to the source of the MOS transistor Q1. Similarly, N-1 N
The channel MOS transistors are connected in series, and the source of the Nth N-channel MOS transistor Qn is connected to the ground potential point 51. IN1 is an inverter having an input terminal connected to the node N1.

When the threshold voltage of the N-channel MOS transistor is V _th , (power supply voltage V _{CC −power} supply voltage V _SS ) is V _th
If it exceeds N times, the burn-in mode is entered. That is,
When the voltage of node N1 exceeds N times V _th , current flows through N channel MOS transistors Q1 to Qn.
Therefore, the voltage of the node N1 becomes V _SS , and the output φBI of the inverter IN1 becomes high level.

FIG. 3 shows an SDR according to the first embodiment of the present invention.
6 is a timing chart for explaining the operation of the control signal buffer command decoder 11a of the AM chip. At time t31, if the signal φBI is at the high level at the rising edge of the clock CLK, the clock CL
The array signal φACT becomes high level for an appropriate time within one cycle of K.

In the memory array control circuit 12, when the array activation signal φACT and the signal φBI are at the high level, the same operation as when the array activation signal φACT and the signal φREF are at the high level is performed. The same effect can be obtained as when the signal φBI applied to the refresh address counter 15 goes high and the signal φREF applied to the refresh address counter 15 goes high. When the signal φBI goes high, the switches 19 and 20 are turned on and the internal address and the internal bank address output from the refresh address counter 15 are output to the internal circuit. That is, the same operation as the auto refresh is performed.

In this way, the burn-in can be executed without requiring any control other than the clock.

Example 2. FIG. 4 is a timing diagram showing the operation of the SDRAM chip according to the second embodiment of the present invention. FIG. 5 is a block diagram showing the structure of the control unit of the SDRAM chip according to the second embodiment. The operation of the controller of the SDRAM chip according to the second embodiment is the same as that of the first embodiment.
The difference from the control unit of the DRAM chip is that the signal φSR is generated when the refresh timer 16 receives the activated signal φBI.
Is the point to output. The self-refresh operation is performed by outputting the signal φSR.

In the SDRAM chip according to the second embodiment, the signal φBI is activated by the burn-in detection circuit 30 when a power supply voltage V _CC sufficiently higher than usual is applied during burn-in. Then, the self-refresh timer 16 is also activated in addition to the various circuits activated in the first embodiment. The self-refresh timer 16 activates the internal refresh address and the array activation signal φACT at regular intervals as in the first embodiment.
According to the SDRAM chip of the second embodiment, the burn-in can be performed without applying the external clock CLK and only by applying the high voltage to the power supply voltage V _CC .

[0038]

As described above, according to the synchronous semiconductor memory device of the first aspect of the present invention, the auto-refresh is activated regardless of the control signal externally input by the power supply voltage. There is an effect that it is possible to perform burn-in even if a burn-in device with a small amount of burn-in is used.

According to the synchronous semiconductor memory device of the second aspect of the invention, the self-refresh is activated regardless of the control signal and the clock input from the outside by the power supply voltage. Even if used, there is an effect that burn-in can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control unit of an SDRAM chip according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a burn-in mode detection circuit according to the first embodiment of the present invention.

FIG. 3 is a timing diagram for explaining burn-in according to the first embodiment of the present invention.

FIG. 4 is a timing diagram for explaining burn-in according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a control unit of an SDRAM chip according to a second embodiment of the present invention.

FIG. 6: Typical packaged 16 MSDR
It is a top view which shows the pin arrangement of AM chip.

FIG. 7 is a block diagram showing a configuration of a control unit of a conventional SDRAM chip.

FIG. 8 is a block diagram showing a configuration of a memory array section of a conventional SDRAM chip.

FIG. 9 is a read / write timing diagram of a general SDRAM.

FIG. 10 is a timing diagram of auto refresh of a general SDRAM.

FIG. 11 is a timing diagram of self-refresh of a general SDRAM.

FIG. 12: 1-bit write / write of general SDRAM
It is a read timing chart.

FIG. 13 is a timing diagram of 1-bit write / read of a standard DRAM.

[Explanation of symbols]

1 SDRAM chip, 10 CLK buffer, 11
Control signal buffer Command decoder, 12 Memory array control circuit, 13 Address buffer, 14
BA buffer, 15 refresh address counter,
16 self-refresh timer, 17 to 20 switch, 21 and 26 memory array, 22 and 27 row decoder, 23 and 28 column decoder, 24 and 29 preamplifier / write buffer, 25 DQ buffer, 30
Burn-in mode detection circuit.

Claims (2)

[Claims] 1. A synchronous semiconductor memory device having an auto-refresh function, when the power supply voltage is higher than a predetermined value, the auto-refresh is automatically synchronized with an external clock regardless of a control signal input from the outside. 1. A synchronous semiconductor memory device characterized by activating a. 2. In a synchronous semiconductor memory device having a self-refresh function, when the power supply voltage is higher than a predetermined value, self-refresh is automatically started regardless of a control signal and a clock input from the outside. And a synchronous semiconductor memory device.