JP2003022698A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory provided with a test mode in which an abnormality in input capacity can be detected without directly measuring the input capacity with a measuring device. SOLUTION: An input buffer circuit 21 includes a differential circuit consisting of P channel MOS transistors 211-213, N channel MOS transistors 214, 215, and a threshold value changing circuit consisting of P channel MOS transistors 217, 218. In the input buffer circuit 21, the threshold value changing circuit is activated at the time of a test mode, current quantity of the N channel MOS transistor 215 is increased, voltage of a node N1 is increased, and the reference voltage VREF is changed equivalently. And, the input buffer circuit 21 compares input voltage DIN of write-in data with the reference voltage VREF, and outputs output data in accordance with the comparison result to an internal circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a synchronous semiconductor memory device which takes in write data from the outside in synchronization with a clock signal periodically applied from the outside.

[0002]

2. Description of the Related Art In recent years, the processing speeds of processing systems such as computer systems and communication systems have become faster and faster, and dynamic random access memory (Dynamic Random Access Memory) used as a main memory in those processing systems has been increasing. The speed of DRAM) is also increasing. Synchronous DRA
M (Synchronous DRAM, hereinafter referred to as SDRAM) is
For example, the address signal and the control signal are fetched and the data is input / output in synchronism with a clock signal which is a system clock. It is not necessary to consider the margin for the skew of the external signal, and the internal operation is performed at high speed. Can be done. However, the operation speed of the DRAM is improved and the microprocessor (MPU) is added.
The operation speed of the DRAM is dramatically improved, and the access time and cycle time of the DRAM become a bottleneck, and the performance of the entire system is being restricted. Therefore, in order to support high-speed MPU in recent years, SDRA
Double data rate SD with twice the data rate of M
RAM (Double Data Rate SDRAM, hereinafter DDR SDR
(Referred to as AM) has been proposed. This is a normal SD
While the RAM uses only the rising edge of the clock signal as the synchronizing signal, the DDR SDRAM uses both the rising edge and the falling edge of the clock signal as the synchronizing signal, and can handle high-frequency input / output signals. It was made possible.

[0003]

As described above, the speed of the semiconductor memory device has been increased, but on the other hand, in the speeded semiconductor memory device, it is important to reduce the input capacitance thereof. Increase. That is, even if the operation of the internal data is speeded up, if the input capacitance of the device is large, the high frequency input data cannot be normally taken in,
After all, such a semiconductor memory device becomes useless.

In the conventional SDRAM, the input capacitance is
The data input / output terminal for inputting / outputting data to / from the outside is allowed within the range of 4.0 pF to 6.5 pF.
However, the input capacity of the DDR SDRAM, which has a data rate twice that of the SDRAM and is capable of high-speed processing, is 4.0 pF to 5.0 p at the data input / output terminal.
It is necessary to keep it within the range of F, and the upper limit of the allowable range is strict.

Against this background, as a problem in increasing the speed of a semiconductor memory device, along with the development of a semiconductor memory device that improves the input capacitance, a semiconductor memory device with an abnormal input capacitance that has increased in importance as described above. Are required to be removed before shipping the product.

Conventionally, the test of the input capacitance has been performed by directly measuring the input capacitance at a data input / output terminal using a measuring device such as an LCR meter. However, with this method, 100% measurement prior to product shipment imposes a large measurement load and is substantially impossible, which is a problem in terms of ensuring the quality of shipped products and quality control during manufacturing.

The present invention has been made to solve the above problems, and an object thereof is a semiconductor memory device capable of detecting an abnormality in the input capacitance without directly measuring the input capacitance with a measuring instrument such as an LCR meter. Is to provide.

[0008]

According to the present invention, a semiconductor memory device is a semiconductor memory device capable of easily detecting an abnormality in input capacitance, and compares an input voltage forming an input signal with a reference voltage, An input buffer circuit that determines the logic of the input signal in accordance with the comparison result and captures it internally, and a control circuit that selectively outputs the test mode activation signal and the test mode deactivation signal to the input buffer circuit. The input buffer circuit changes the reference voltage from the normal operation according to the test mode activation signal and compares the input voltage with the reference voltage.

Preferably, the input buffer circuit compares an input voltage with a reference voltage and outputs an output voltage which determines the logic of the input signal according to the comparison result, and a test mode activation signal. And a threshold changing circuit that is activated by changing the reference voltage from the normal operation.

Preferably, the threshold value changing circuit is connected to the differential circuit so that the amount of current of the MOS transistor receiving the input voltage at its gate terminal becomes larger than that in the normal operation in response to the test mode activation signal.

Preferably, the threshold value changing circuit is connected to a power supply node to which the differential circuit is connected and an output node of the differential circuit.

[0012] Preferably, the threshold value changing circuit receives a test mode activating signal at a gate terminal to activate the threshold value changing circuit, and a first conductivity type first MOS transistor and a second conductivity type MOS transistor. And a second MOS transistor of the first conductivity type that increases the amount of current of the MOS transistor that receives the input voltage at its gate terminal.

Preferably, the threshold value changing circuit is connected to a ground node to which the differential circuit is connected and a node on the high potential side connected to the second MOS transistor receiving the reference voltage at its gate terminal.

Preferably, the threshold value changing circuit receives a test mode activating signal at its gate terminal to activate the threshold value changing circuit, and a second conductive type third MOS transistor and a second conductive type MOS transistor. And a fourth MOS transistor of the second conductivity type that reduces the amount of current of the second MOS transistor receiving the reference voltage at the gate terminal.

Preferably, the threshold value changing circuit is connected to the differential circuit so that the amount of current of the MOS transistor receiving the input voltage at its gate terminal is smaller than that in the normal operation in response to the test mode activation signal.

Preferably, the threshold value changing circuit is connected to a power supply node to which the differential circuit is connected and a node on the high potential side which is connected to the second MOS transistor receiving the reference voltage at its gate terminal.

Preferably, the threshold value changing circuit receives a test mode activation signal at its gate terminal to activate the threshold value changing circuit, and a first conductivity type first MOS transistor and a second conductivity type MOS transistor. And a second MOS transistor of the first conductivity type that increases the amount of current of the second MOS transistor receiving the reference voltage at the gate terminal.

Preferably, the threshold value changing circuit is connected to a ground node to which the differential circuit is connected and an output node of the differential circuit.

Preferably, the threshold value changing circuit receives a test mode activation signal at its gate terminal to activate the threshold value changing circuit, and a second conductivity type first MOS transistor and a second conductivity type MOS transistor. And a second MOS transistor of the second conductivity type that reduces the amount of current of the MOS transistor that receives an input voltage at its gate terminal.

According to the semiconductor memory device of the first to twelfth aspects, it is possible to eliminate an abnormal input capacitance without applying a test load without using a measuring instrument. Input capacitance test can be done. As a result, the semiconductor memory device having an abnormal input capacity can be surely removed before the product is shipped, the quality control can be strengthened, and a high quality product can be supplied to the market.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts will be denoted by the same reference characters and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a block diagram showing a schematic structure of a semiconductor memory device 1 according to the present invention.

Referring to FIG. 1, semiconductor memory device 1 includes a clock buffer circuit 6 which receives complementary clock signals CLK and / CLK from the outside, and address signals A0 to A0 from the outside.
An address buffer circuit 5 receiving Ai and a control signal buffer circuit 7 receiving a control signal including a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE from the outside.

Clock buffer circuit 6 latches complementary clock signals CLK and / CLK received from the outside and outputs a clock signal.

Address buffer circuit 5 latches address signals A0-Ai received from the outside and outputs the address signal in synchronization with clock signals CLK and / CLK.

Control signal buffer circuit 7 receives a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / W which are externally received.
It latches E and outputs the control signal in synchronization with the clock signals CLK and / CLK.

The semiconductor memory device 1 further includes a control circuit 4
, Memory array 3, row decoder 9, and column decoder 1
0, bit line pair 8, and input / output buffer circuit 2.

Control circuit 4 outputs address signals A0-Ai output from address buffer circuit 5 and control signal buffer circuit 7 in synchronization with clock signals CLK and / CLK output from clock buffer circuit 6. Row address strobe signal / RAS, column address strobe signal / CAS, write enable signal /
Receive WE. Then, the control circuit 4 receives the address signal A fetched by the address buffer circuit 5 in accordance with the combination of the logical levels of the control signals received from the control signal buffer circuit.
It is determined whether 0 to Ai are row address signals or column address signals. When address signals A0 to Ai are row address signals, control circuit 4 outputs a signal for activating row decoder 9 to row decoder 9.

When row decoder 9 is activated in response to an activation signal received from control circuit 4, row decoder 9 takes in address signals A0-Ai from address buffer circuit 5, and a memory array corresponding to the address signals A0-Ai. Activate the word line above 3.

On the other hand, when address signals A0 to Ai are column address signals, control circuit 4 outputs a signal for activating column decoder 10 to column decoder 10.

When column decoder 10 is activated in response to the activation signal received from control circuit 4, column decoder 10 takes in address signals A0-Ai from address buffer circuit 5, and a memory array corresponding to the address signals A0-Ai. Bit line pair 8 on 3 is activated.

In this way, the address signals A0-Ai
The memory cells on the memory array 3 corresponding to are activated.

A plurality of bit line pairs 8 provided on memory array 3 are connected to a plurality of memory cells on memory array 3 and input / output data to / from the memory cells.

The input / output buffer circuit 2 includes an input buffer circuit 21 and an output buffer circuit 22.

The input buffer circuit 21 has a complementary data strobe signal D serving as a reference for reading data DQ0 to DQn and data DQ0 to DQn from the outside.
Receive QS and / DQS. And the input buffer circuit 21
Is an internal data ID via a sense amplifier (not shown)
Q0 to IDQn are output to the bit line pair 8. The input buffer circuit 21 will be described in detail later.

The output buffer circuit 22 receives internal data IDQ from the bit line pair 8 via a sense amplifier (not shown).
0 to IDQn are received and externally output complementary data strobe signals DQS and / DQS which serve as a reference for the read timing of data DQ0 to DQn and data DQ0 to DQn.

Input / output buffer circuit 2 receives from control circuit 4 an activation signal / EN for activating input / output buffer circuit 2 and a test mode activation signal / TMEN for activating semiconductor memory device 1 in the test mode. receive.

Referring to FIG. 2, a series of operations in which semiconductor memory device 1 takes in write data DQ0 to DQn from the outside and writes the data to the memory cells on memory array 3 will be described.

All signals from the outside are taken in in synchronization with the clock signal CLK received from the outside.

Control signal buffer circuit 7 sets row address strobe signal / RAS to L (logical low) level at the rising edge of clock signal CLK at time t1.
When the column address strobe signal / CAS and the write enable signal / WE are taken in as H (logical high) level, the external address signal Add (Add represents A0 to Ai together) taken in by the address buffer circuit 5 is given as a row address. A signal is output to the control circuit 4 so that it is recognized as Xa. Upon receiving the signal from the control signal buffer circuit 7, the control circuit 4 activates the word line on the memory array 3 corresponding to the row address Xa received from the address buffer circuit 5 and performs a row selection operation.

At time t2, control signal buffer circuit 7 takes in row address strobe signal / RAS as H level, column address strobe signal / CAS and write enable signal / WE as L level at the rising edge of clock signal CLK. , The external address signal Add fetched by the address buffer circuit 5 is set to the column address Y.
A signal is output to the control circuit 4 so as to be recognized as b.
Upon receiving the signal from the control signal buffer circuit 7, the control circuit 4 receives the column address Y received from the address buffer circuit 5.
The bit line pair 8 on the memory array 3 corresponding to b is activated and a column selection operation is performed.

At the time t2, the row address strobe signal / RAS and the column address strobe signal / RAS
The state of the combination of CAS and the write enable signal / WE indicates the writing of data, and the input buffer circuit 21 sequentially takes in the data d0 to d3 from this time t2. The data is taken in in synchronization with the rising or falling of data strobe signal DQS taken in by input buffer circuit 21 in synchronization with clock signal CLK.

Each of the above-mentioned control signals fetched from the outside is fetched at the cross points of complementary clock signals CLK and / CLK. In addition, data D / Q (D / Q
Represents the data DQ0 to DQn together) is a complementary data strobe signal DQS,
Captured at the / DQS crosspoint.

It should be noted that in FIG. 2, the number of data that is continuously taken in is called a burst length, and in this example, the burst length is 4. For example, when the data D / Q is fetched from the eight data input / output terminals as 8-bit continuous data of DQ0 to DQ7, if the burst length is 4, the total is 32.
Bit data is continuously captured.

Input buffer circuit 21, when taking in data d0, outputs an output voltage corresponding to the logic level of data d0 to a sense amplifier (not shown), and writes data d0 into bit line pair 8. As a result, the data d0 is written in the memory cell activated by the row selecting operation and the column selecting operation. After that, data d1 to d3 continuing for the burst length
However, the data is sequentially written from the memory cell in which the data d0 is written to successive memory cells.

At time t3, the clock signal C
The row address strobe signal / RAS and the write enable signal / WE are at the L level and the column address strobe signal / CAS is at the H level in synchronization with the rising edge of LK.
When taken in as a level, rewriting (precharge) to the memory cell is performed.

The operation of reading data D / Q from semiconductor memory device 1 is almost the same as the operation of writing. That is, the row address strobe signal / RAS,
A row selection operation and a column selection operation are performed according to a control signal including a column address strobe signal / CAS and a write enable signal / WE and an address signal Add,
The data of the selected memory cell is output to the output buffer circuit 2 via the bit line pair 8 and the sense up (not shown).
Output to outside by 2.

Next, the configuration of the input buffer circuit 21 including the characteristic circuit of the present invention will be described with reference to FIG. The input buffer circuit 21 has a current mirror type circuit configuration. Input buffer circuit 21 uses input buffer circuit activation signal / EN received from control circuit 4 as a gate drive voltage, and power supply node 210 (voltage VDD).
A P-channel MOS transistor 211 connected to
One data DQi of externally input data DQ0 to DQn
Input voltage DIN as a gate drive voltage and an N channel MOS transistor 215 connected to the ground node, and a reference voltage VREF as a gate drive voltage, an N channel MOS transistor 214 connected to the ground node and a P channel MOS transistor 211. A P-channel MOS transistor 212 connected between the N-channel MOS transistor 214 and the N-channel MOS transistor 214 and having a gate drive voltage at the voltage of the connection node N2 with the N-channel MOS transistor 214
P-channel MOS transistor 211 and N-channel MO
A P-channel MOS transistor 213 connected between the S-transistor 215 and the gate drive voltage of the node N2, and a connection node N between the P-channel MOS transistor 213 and the N-channel MOS transistor 215.
1 and a buffer 216 connected to 1. P channel M
OS transistor 211 is turned on when activation signal / EN received from control circuit 4 is at L level to activate input buffer circuit 21, and also operates as a constant current source. Further, the buffer 216 operates as a drive buffer which is driven according to the voltage of the node N1.

Input buffer circuit 21 further uses test mode activating signal / TMEN received from control circuit 4 as a gate drive voltage, and P channel MOS transistor 217 connected to power supply node 210 and P channel MOS transistor.
A P-channel MO that is connected between the transistor 217 and the node N1 and uses the voltage of the node N2 as a gate drive voltage.
S-transistor 218.

The input buffer circuit 21 is provided for the input data (n + if the input data is DQ0 to DQn).
1), and data strobe signals DQS and / DQ
S is also taken in by the input buffer circuit 21.

The operation of the input buffer circuit 21 will be described below. H-level test mode activation signal /
During normal operation when TMEN is input, the input buffer circuit 21 is a current mirror type input circuit generally used as an input buffer circuit of DRAM. Now, the W / L of the P-channel MOS transistor 212 (W
Is the channel width and L is the channel length) and the W / L ratio of the N-channel MOS transistor 214 is W / L of the P-channel MOS transistor 213 and the N-channel MOS transistor 213.
If the W / L ratio of the transistor 215 is the same, the input voltage DIN, which is the gate drive voltage of the N-channel MOS transistor 215, becomes the N-channel MOS transistor 21.
When it is equal to the reference voltage VREF which is the gate drive voltage of 4, the voltage of the node N1 becomes 1/2 VDD. When the input voltage DIN changes from the reference voltage VREF, the voltage of the node N1 changes from 1/2 VDD according to the differential voltage. That is, when the input voltage DIN is higher than the reference voltage VREF, the voltage of the node N1 becomes lower than 1/2 VDD, and when the input voltage DIN is lower than the reference voltage VREF, the voltage of the node N1 becomes higher than 1/2 VDD. Therefore, if the threshold value of the buffer 216 is set to 1/2 VDD, the reference voltage VREF is applied to the output of the buffer 216.
Is the threshold of the input voltage DIN.

Next, the operation when the test mode activation signal / TMEN received from control circuit 4 is at L level and the test mode is activated will be described. P-channel MOS transistor 217 operates as a constant current source when test mode activation signal / TMEN is at L level. The P-channel MOS transistor 218 has the same gate drive voltage as that of the P-channel MOS transistor 213, and supplies the current amount flowing through the P-channel MOS transistor 213 at a constant ratio to the node N1.

At this time, the voltage of the node N1 is set to 1/2 VD
In order to achieve D, it is necessary to increase the amount of current flowing through the N-channel MOS transistor 215.
Since the transistor 215 has a bias point set so as to operate in the saturation region, it is necessary to increase DIN, which is the gate drive voltage of the N-channel MOS transistor 215. That is, the amount of voltage to be increased is Δv
Then, in the test mode, the reference voltage is VREF + Δ
can be considered to be v.

It should be noted that this voltage amount Δv is the P channel MO
S transistors 217, 218 and P channel MOS
It depends on the size of the transistor 213. FIG. 4 is a diagram showing how Δv is determined. Referring to FIG. 4, the horizontal axis represents the gate drive voltage in each MOS transistor, and the vertical axis represents the amount of current flowing in each MOS transistor.
Represents the amount of current of the P-channel MOS transistor 213, the curve 41 represents the total amount of current of the P-channel MOS transistor 213 and the P-channel MOS transistor 218, and the curve 42 represents the amount of current of the N-channel MOS transistor 215. Intersection 4 between curves 40 and 41 and curve 42
N-channel MOS transistor 215 in 3, 44
The gate drive voltage of ½ the voltage at node N1
The input voltage DIN becomes VDD. That is, in the test mode, the P-channel MOS transistors 218 to P
Since the additional current is supplied to the channel MOS transistor 215, the output voltage at the node N1 is reduced to 1/2 VDD.
The input voltage DIN that is to be shifted from the voltage at the intersection 43 to the voltage at the intersection 44 by Δv.

Referring again to FIG. 1, input data DQ0-DQn and data strobe signals DQS, / DQS taken into semiconductor memory device 1 are taken into semiconductor memory device 1 as a voltage. For example, when the voltage is higher than the predetermined value, the logic level of the input data is the H level, and when the voltage is lower than the predetermined value, the logic level of the input data is the L level, and semiconductor memory device 1 takes in the data. Since the input voltage of the input data has the input capacity of the semiconductor memory device 1, it has a change rate according to the input capacity when changing.

Referring to FIG. 5, there is shown a time change of the input voltage when the input data is taken into semiconductor memory device 1 as a voltage input. The curve 50 shows that the input voltage is from L level to H
Curve 51 shows when the input voltage changes from H level to L level. Straight line 52
Indicates the reference voltage VREF in the input buffer circuit 21, and the input buffer circuit 21 for the input data depends on whether the input voltage exceeds the reference voltage VREF.
The logic level of the output of switches. The straight line 53 indicates the threshold value of the input voltage that switches the logic level of the output of the input buffer circuit 21 in the test mode. As shown in FIG. 5, in the test mode, the timing at which the logic level of the output of the input buffer circuit 21 is switched with respect to the same input voltage is shifted by the time difference Td as compared with the normal operation. That is, when the input voltage is switched from the L level to the H level, the output logic level is set to the time Td as compared with the normal operation.
Only switch slowly. Further, when the input voltage switches from the H level to the L level, the output logic level switches earlier by the time Td than in the normal operation.

Referring to FIG. 6, in semiconductor memory device 1, input buffer circuit 21 causes data strobe signal DQS.
3 shows signal waveforms when taking in data D / Q. The input buffer circuit 21 takes in the voltage of the data strobe signal DQS, and at time t1, the voltage is the reference voltage VR.
When it exceeds EF, the input buffer circuit 21 receives the data D / Q.
Take in. At that time, in consideration of the skew of the data D / Q, the data D / Q needs to be fixed to the H level before being fetched in response to the rise of the data strobe signal DQS. The time until the setting is called the data setup time tDS. Similarly, the data D / Q needs to be held for a certain time even after being taken in according to the rising of the data strobe signal DQS.
The holding time is called the data hold time tDH. The polygonal lines 60 to 62 show the state of the skew when the data D / Q falls at the time t1, the polygonal line 60 shows a typical timing, and the polygonal line 61 shows the time until the data D / Q is read. The timing when the margin is maximum,
The broken line 62 shows the timing when the time margin until the data D / Q is read is the minimum.

When the test mode is activated, the reference voltage for taking in the data strobe signal DQS and the data D / Q increases from the level of the straight line 63 to the level of the straight line 64 by Δv. Here, paying attention to the data hold time tDH at the time t1 when the data strobe signal DQS rises from the L level to the H level, the timing at which the logic level of the output for the data strobe signal DQS is switched is delayed by Td from the time of the normal operation. At this time, if the voltage level of the data D / Q is at the H level, the data D / Q
When D falls from H level to L level, data D / Q
Since the switching timing of the logic level of the output for is earlier than that in the normal operation by Td, the data hold time is tDH2 = tDH-2Td. On the other hand, time t
1, when the voltage level of the data D / Q is at the L level, the timing at which the logical level of the output for the data strobe signal DQS is switched is Td more than that in the normal operation.
However, the data hold time is tDH1 = tDH and does not change because the timing at which the output logic level for the data D / Q is switched is also delayed by Td.

Next, paying attention to the data setup time tDS at the time t2 when the data strobe signal DQS falls from the H level to the L level, the timing at which the logic level of the output with respect to the data strobe signal DQS is switched is Td. Just get ahead. At this time, if the voltage level of the data D / Q is at the L level, the data D
When / Q rises from L level to H level, data D
Since the switching timing of the output logic level with respect to / Q is delayed by Td from the time of normal operation, the data setup time is tDS2 = tDS-2Td. On the other hand, when the voltage level of the data D / Q is at the H level at the time t2, the timing at which the logical level of the output for the data strobe signal DQS is switched is advanced by Td compared to the time of the normal operation, but the output for the data D / Q is output. Since the timing of switching the logic level of is also advanced by Td, the data setup time is tDS1 = tDS and does not change.

On the other hand, this data setup time tDS
Alternatively, the time change 2Td of the data hold time tDH is
It depends on the rate of change of the input voltage. That is, referring to FIG. 7, in a straight line 70 having a large change rate of the input voltage and a straight line 71 having a small change rate, Td1 <Td2.
Becomes If the conditions are the same, this time change 2Td is
It is proportional to the input capacity of the semiconductor memory device 1. That is, the larger the input capacitance, the larger the time change 2Td.

Referring again to FIG. 1, when data DQ0 to DQn and data strobe signals DQS and / DQS are taken in semiconductor memory device 1, test mode is activated to set data setup time tDS or data hold time tDH. When measured, as described above, the data setup time tDS or the data hold time t that changes by 2Td depending on the input capacitance from the measured value during normal operation.
DH is measured. Therefore, in the semiconductor memory device 1, the input capacitance is determined by measuring the change in the data setup time tDS or the data hold time tDH.

As described above, the equivalent change Δv in the reference voltage VREF is determined by the P-channel MOS transistor 217, which supplies an additional current to the N-channel MOS transistor 215.
218 and the size of the P-channel MOS transistor 213. Therefore, the size of the P-channel MOS transistors 217 and 218 is determined in advance by simulation or the like so that Δv becomes a predetermined amount (about 0.1 to 0.3 V). Then, in the plurality of semiconductor memory devices 1 in which the P-channel MOS transistors 217 and 218 having the determined size are incorporated, the input capacitance is measured by a measuring device such as an LCR meter, and the data setup when the test mode is activated. The values of the time tDS and the data hold time tDH are measured, and the correlation with the measured input capacitance is obtained. The data setup time tDS and the data hold time tD when the input capacitance is abnormal
The determination point of H is determined from the obtained correlation.
As a result, the test mode is activated in the semiconductor memory device 1, the data setup time tDS and the data hold time tDH are measured, and the semiconductor memory having an input capacity exceeding a predetermined capacity is determined by comparing with a predetermined determination point. Device 1 is eliminated.

In the above-mentioned embodiment, P
The channel MOS transistors 217 and 218 are arranged in parallel with the P-channel MOS transistors 211 and 213 to increase the amount of current of the N-channel MOS transistor 215, and the reference voltage VREF is equivalently increased by Δv.
The circuit may be configured to reduce the current amount of the N-channel MOS transistor 214, and the reference voltage VREF may be raised equivalently by Δv. In this case, the input buffer circuit 21 is used instead of the input buffer circuit 21.

Referring to FIG. 8, input buffer circuit 21A
, N-channel MOS operating as a constant current source
Transistor 219 is connected between N channel MOS transistors 214 and 215 and the ground node. N-channel MOS transistors 220 and 221 are circuits for reducing the amount of current of N-channel MOS transistor 214, and N-channel MOS transistor 220 inverts test mode activation signal / TMEN received from control circuit 4 to the gate drive voltage. The signal TMEN
N-channel MOS transistor 221 receives a reference voltage as a gate drive voltage.

In semiconductor memory device 1 having input buffer circuit 21A, when the test mode is activated, the amount of current of N channel MOS transistor 214 in input buffer circuit 21A decreases and the voltage of node N2 decreases. Therefore, the P-channel MOS transistor 21
Since the gate drive voltages of 2 and 213 decrease, the amount of current of P channel MOS transistor 213 increases. That is, the amount of current of N channel MOS transistor 215 increases. Therefore, like the circuit shown in FIG. 3, in order to set the voltage at the node N1 to 1/2 VDD, the input voltage needs to be VREF + Δv, and the same operation as the circuit shown in FIG. 3 can be obtained. After that, the input capacitance can be tested according to the same procedure as described above.

As described above, according to the first embodiment, the LC
Since the semiconductor memory device 1 having an input capacity exceeding a predetermined capacity can be eliminated without using a measuring device such as an R meter, the total number of input capacities for shipped products, which was substantially impossible by the measuring device method. Tests can be realized and defective products can be reliably eliminated.

[Second Embodiment] In the first embodiment, the semiconductor memory device 1 equivalently raises the reference voltage VREF to be compared with the voltage of the input data by Δv, but in the second embodiment, the reference voltage VREF is increased. The voltage VREF is equivalently Δv
A semiconductor memory device that is lowered only by a certain amount will be described.

As the configuration of the semiconductor memory device in the second embodiment, the configuration of semiconductor memory device 1 is used as it is.
As the input buffer circuit, the input buffer circuit 21B is used instead of the input buffer circuits 21 and 21A.

Referring to FIG. 9, input buffer circuit 21B
Is an N-channel MOS transistor 219 that operates as a constant current source.
Connected between 215 and the ground node. N channel M
The OS transistor 220 and the N-channel MOS transistor 222 are the N-channel MOS transistor 215.
Is a circuit for reducing the amount of current of the N channel M
The OS transistor 220 uses the gate drive voltage for the control circuit 4
N-channel MOS transistor 222 receives a data input voltage DIN as a gate drive voltage of TMEN which is a signal obtained by inverting test mode activation signal / TMEN.

In the semiconductor memory device 1 having the input buffer circuit 21B, when the test mode is activated, the current flowing into the N channel MOS transistor 215 is reduced because it is shunted via the N channel MOS transistors 220 and 222. However, the voltage of the node N1 decreases. Therefore, the voltage at the node N1 is 1/2 V
In order to set DD, it is necessary to set the input voltage DIN to VREF−Δv.

Therefore, referring again to FIG. 5, in the input buffer circuit 21B, when the test mode is activated, the threshold value of the input voltage for switching the logical level of the output of the input buffer circuit 21B is from the level of the straight line 52. Transition to the level of the straight line 54. Therefore, when the input voltage switches from the L level to the H level, the output logical level switches earlier by the time Td than in the normal operation, and the input voltage becomes the H level.
When the level is switched to the L level, the output logic level is switched later by the time Td than in the normal operation.

Therefore, although not shown, paying attention to the data setup time tDS at the time t1 when the data strobe signal DQS rises from the L level to the H level, the timing at which the logic level of the output with respect to the data strobe signal DQS is switched during the normal operation. It is faster than Td by Td. At this time, if the voltage level of the data D / Q is at the H level, when the data D / Q falls from the H level to the L level, the switching timing of the output logic level for the data D / Q is more than that in the normal operation. Is also delayed by Td, the data setup time is tDS2 = t, where tDS is the data setup time during normal operation.
It becomes DS-2Td. On the other hand, data D at time t1
When the voltage level of / Q is at the L level, the timing at which the output logic level for the data strobe signal DQS is switched is earlier than that during normal operation by Td, but the timing at which the output logic level for the data D / Q is switched. Also, since Td is advanced by Td, the data setup time is t
DS1 = tDS and does not change.

Next, paying attention to the data hold time tDH at the time t2 when the data strobe signal DQS falls from the H level to the L level, the timing at which the logical level of the output for the data strobe signal DQS is switched is Td. Just delayed. At this time, if the voltage level of the data D / Q is at the L level, the data D / Q
When D goes from L level to H level, data D / Q
Since the switching timing of the logic level of the output with respect to is earlier than that in the normal operation by Td, the data hold time is tDH2 = tDH-2Td when the data hold time in the normal operation is tDH. On the other hand, time t
2, when the voltage level of the data D / Q is at the H level, the timing at which the logic level of the output for the data strobe signal DQS is switched is Td more than in the normal operation.
However, the data hold time is tDH1 = tDH and does not change because the timing at which the output logic level for the data D / Q is switched is also delayed by Td.

Therefore, as described in the description of the first embodiment, the input capacitance, the data setup time tDS when the test mode is activated, and the data hold time tDH are collected in advance for a plurality of semiconductor memory devices 1. If the correlation is obtained in this way, the semiconductor memory device 1 having an input capacity exceeding the predetermined capacity can be excluded from the correlation.

In input buffer circuit 21B, N-channel MOS transistor 220 and N-channel MOS transistor 222 reduce the amount of current of N-channel MOS transistor 215 to reduce reference voltage VRE.
Although F is equivalently lowered by Δv, the reference voltage VREF may be equivalently lowered by Δv by configuring the circuit so as to increase the current amount of the N-channel MOS transistor 214. In this case, the input buffer circuit 21C is used instead of the input buffer circuit 21B.

Referring to FIG. 10, input buffer circuit 21
In C, the circuit including the P-channel MOS transistors 217 and 218 in the input buffer circuit 21 is
It is connected to node N2 so as to increase the amount of current of channel MOS transistor 214.

In this case, when the test mode is activated,
The amount of current of N channel MOS transistor 214 increases and the voltage of node N2 increases. Therefore, the gate drive voltage of the P channel MOS transistors 212 and 213 increases, so that the P channel MOS transistor 21
The current amount of 3 decreases. That is, the amount of current of N channel MOS transistor 215 decreases. Therefore, similarly to the circuit shown in FIG. 9, in order to set the voltage at the node N1 to 1/2 VDD, the input voltage DIN is set to VREF−.
It is necessary to set Δv, and the same operation as the circuit shown in FIG. 9 can be obtained. After that, the input capacitance can be tested according to the same procedure as described above.

As described above, according to the second embodiment as well, the semiconductor memory device 1 having an input capacity exceeding a predetermined capacity is eliminated without using a measuring device such as an LCR meter as in the first embodiment. Therefore, it is possible to realize a 100% test of the input capacitance with respect to the shipped product, which was substantially impossible by the method using the measuring instrument, and it is possible to reliably exclude defective products.

In the above-described first and second embodiments, the test mode is activated when the data strobe signal DQS and the data D / Q are fetched, but the data strobe signal DQS or the data D / Q is not activated. The test mode may be activated for only one of the inputs. In this case, the data setup time tDS and the data hold time tDH change from the normal operation by Td.

Further, in the semiconductor memory device 1 described in the first and second embodiments, if the input capacitance test is performed on-spec with the data setup time tDS and the data hold time tDH with the test mode still active, it is required. It is possible to perform a test that is more strict with respect to the specified specifications, that is, has a margin with respect to the specifications.

In the first and second embodiments described above, the input buffer circuit for fetching data from the outside has been described. However, a signal is received from the outside, the signal is compared with a reference voltage, and the comparison is performed. If it is a buffer circuit that determines the logic of the signal according to the result and takes it in, the same effect can be obtained with the same circuit configuration as the input buffer circuit described above. That is, in the address buffer circuit 5 in FIG. 1, if the data strobe signal DQS is replaced by the clock signal / CLK and the data signal D / Q is received from the outside by the address signals A0 to Ai in the description of the first and second embodiments, the operation is performed. It is possible to obtain the same effects as those described in the first and second embodiments. Further, also in the control signal buffer circuit 7 in FIG.
Similarly, the data strobe signal DQS is changed to the clock signal / C.
If LK and the row address strobe signal / RAS, the column address strobe signal / CAS or the write enable signal / WE which receives the data signal D / Q from the outside are replaced, the same effect as described in the first and second embodiments can be obtained. The effect can be obtained.

The embodiments disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to the present invention.

FIG. 2 is a signal waveform diagram illustrating an operation at the time of writing data in the semiconductor memory device shown in FIG.

FIG. 3 is a circuit diagram of the input buffer circuit shown in FIG.

FIG. 4 is a diagram for explaining that the reference voltage equivalently changes by Δv.

FIG. 5 is a diagram showing a change with time of an input voltage.

FIG. 6 is an operation waveform diagram showing an operation of input data of the semiconductor memory device.

FIG. 7 is a diagram showing a time change of an input voltage in semiconductor memory devices having different input capacitances.

FIG. 8 is another circuit diagram of the input buffer circuit shown in FIG.

9 is another circuit diagram of the input buffer circuit shown in FIG. 1. FIG.

10 is another circuit diagram of the input buffer circuit shown in FIG. 1. FIG.

[Explanation of symbols]

1 semiconductor memory device, 2 input / output buffer circuit, 3 memory array, 4 control circuit, 5 address buffer circuit, 6 clock buffer circuit, 7 control signal buffer circuit, 8 bit line pair, 21, 21A to 21C input buffer circuit, 22 Output buffer circuit, 210 power supply node, 211-213, 217, 218 P-channel MOS
Transistors, 214, 215, 219 to 222 N-channel MOS transistors, 216 buffers, N1,
N2 node.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 11/409 G01R 31/28 B H01L 21/66 W D F term (reference) 2G132 AA08 AB01 AC03 AD01 AG08 AK09 AL31 4M106 AA01 AC08 5L106 AA01 DD00 DD11 EE03 5M024 AA91 BB03 BB40 DD32 DD33 DD35 DD83 HH01 JJ02 MM04 MM10 PP01 PP03 PP07 PP09

Claims (12)

[Claims] 1. A semiconductor memory device capable of easily detecting an abnormality in input capacitance, wherein an input voltage forming an input signal is compared with a reference voltage, and the logic of the input signal is determined according to the comparison result. An input buffer circuit that is internally taken in; and a control circuit that selectively outputs a test mode activation signal and a test mode deactivation signal to the input buffer circuit, wherein the input buffer circuit is the test mode activation signal A semiconductor memory device, wherein the reference voltage is changed from a normal operation according to a signal to compare the input voltage with the reference voltage. 2. The input buffer circuit compares the input voltage with the reference voltage and outputs an output voltage that determines the logic of the input signal according to the comparison result, and the test mode activation circuit. The semiconductor memory device according to claim 1, further comprising a threshold value changing circuit that is activated in response to an activation signal and changes the reference voltage from a normal operation time. 3. The threshold value changing circuit is connected to the differential circuit so that the amount of current of a MOS transistor receiving the input voltage at its gate terminal is made larger than that in normal operation in response to the test mode activation signal. The semiconductor memory device according to claim 2, wherein the semiconductor memory device comprises: 4. The semiconductor memory device according to claim 3, wherein the threshold value changing circuit is connected to a power supply node to which the differential circuit is connected and an output node of the differential circuit. 5. The first MOS of a first conductivity type, wherein the threshold value changing circuit receives the test mode activating signal at a gate terminal and activates the threshold value changing circuit.
5. The transistor according to claim 4, comprising a transistor and a second MOS transistor of a first conductivity type that increases the amount of current of the MOS transistor of a second conductivity type that receives the input voltage at its gate terminal. Semiconductor memory device. 6. The threshold value changing circuit is connected to a ground node to which the differential circuit is connected and a high potential side node connected to a second MOS transistor having a gate terminal receiving the reference voltage. The semiconductor memory device according to claim 3. 7. The third MOS of the second conductivity type, wherein the threshold value changing circuit receives the test mode activating signal at a gate terminal and activates the threshold value changing circuit.
7. A transistor and a fourth MOS transistor of a second conductivity type, which is a MOS transistor of a second conductivity type and reduces the amount of current of the second MOS transistor which receives the reference voltage at its gate terminal. The semiconductor memory device according to 1. 8. The threshold value changing circuit is connected to the differential circuit so that the amount of current of a MOS transistor receiving the input voltage at its gate terminal is smaller than that in normal operation in response to the test mode activation signal. The semiconductor memory device according to claim 2, wherein the semiconductor memory device comprises: 9. The threshold value changing circuit is connected to a power supply node to which the differential circuit is connected, and a high potential side node connected to a second MOS transistor having a gate terminal receiving the reference voltage. The semiconductor memory device according to claim 8. 10. The first conductivity type first MOS which activates the threshold value changing circuit by receiving the test mode activating signal at a gate terminal of the threshold value changing circuit.
10. A transistor and a second MOS transistor of a first conductivity type which increases the amount of current of the second MOS transistor which is a second conductivity type MOS transistor and receives the reference voltage at its gate terminal. The semiconductor memory device according to 1. 11. The semiconductor memory device according to claim 8, wherein the threshold value changing circuit is connected to a ground node to which the differential circuit is connected and an output node of the differential circuit. 12. The first conductivity type first MOS which receives the test mode activating signal at a gate terminal and activates the threshold changing circuit.
12. The transistor according to claim 11, comprising a transistor and a second MOS transistor of a second conductivity type, which is a MOS transistor of a second conductivity type and reduces a current amount of the MOS transistor whose gate terminal receives the input voltage. Semiconductor memory device.