JPS63266689A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up an operation by overlapping the operation period of a charge circuit and the operation period of a selection circuit at least by a part of them. CONSTITUTION:A semiconductor memory is provided with plural memory cells MC, provided at the intersection points of data lines D0, the inverse of D0, and plural word lines W0, W1-Wn respectively, and the charge circuit PC for giving a prescribed potential to the data lines D0, the inverse of D0 as synchronizing with a timing signal, and the selection circuit DS for selecting the prescribed word line out of the plural word lines W0, W1-Wn as synchronizing with a select signal to select the semiconductor memory. Then, the operation period of the charge circuit PC and the operation period of the selection circuit DS are made to overlap each other at least by a part of them. Thus, because the memory cell can be accessed without providing any special precharging period, a memory cycle can be shortened, and the speed up of the operation can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and for example, to a technique that is effective when used in a static RAM (random access memory).

[Conventional technology]

MOS (metal oxide semiconductor)
uctor: metal oxide film semiconductor) static type RA
The memory cell in M is composed of, for example, a static type 7 lip-flop circuit consisting of a pair of drive MOSFETs whose gates and drains are cross-coupled and their load elements, and a pair of transmission MOSFETs. The memory play includes a plurality of memory cells arranged in a matrix and a plurality of pairs of complementary data lines, and each complementary data line is coupled to an input/output terminal of a memory cell to be associated with it.

It is necessary to set the potential of the complementary data line to a predetermined voltage at least before reading memory cell information.

There are two methods for setting the complementary data line to a predetermined constant voltage: one is to use a divided voltage obtained by supplying a steady current to a resistor provided between the power supply voltages, and the other is to pre-charge the parasitic capacitance of the data set. There is a way to charge. In the latter precharge method, when steady state electrolysis is selected, there is a risk that the information stored in the memory cell may be destroyed by the low level caused by the natural discharge of the complementary data line.

Regarding the static type RAM, see, for example, Japanese Patent Laid-Open No. 198594/1983.

[Problem that the invention seeks to solve]

One purpose of this proposal is to provide a static ffiRAM that achieves high-speed operation.

Another object of the present invention is to provide a semiconductor memory device that can create all word lines in a non-selected state with a simple configuration.

[Means for solving problems]

A brief summary of the five representative inventions disclosed in this application is as follows.

The semiconductor memory includes a plurality of memory cells each provided at the intersection of a data line and a plurality of word lines, a charge circuit for applying a predetermined potential to the data line in synchronization with a timing signal, and a semiconductor memory. a selection circuit for selecting a predetermined word line from among the plurality of word lines in synchronization with a selection signal, such that an operating period of the charging circuit and an operating period of the selection circuit overlap at least in part. be made into

[Effect]

According to the above-described means, memory cells can be accessed without providing a special precharge period, so the memory cycle can be shortened. In other words, it is possible to speed up the operation.

〔Example〕

FIG. 1 shows a static RAM to which this invention is applied.
1 is a plan view of one semiconductor integrated circuit (IC) chip in which ( , SRAM') is formed; FIG. A wire bonding pad BP and a corresponding I10 buffer are provided in the peripheral area within the IC chip. I10
The buffer takes in a signal applied to the internal area of the IC chip from outside the IC'Deg, and sends a signal supplied from the internal area of the IC chip to the outside of the I10 chip. Although not particularly limited, the internal area of this IC chip is
It is formed by an arithmetic circuit unit EU, an instruction/memory access control unit IU, an operand control unit 0U11, an interrupt control unit SU, and a microinstruction/scan control unit QU. S.R.A.
M is provided in the arithmetic circuit section and is mainly used as a register for arithmetic operations.

FIG. 2 is a layout diagram of the SRAM shown in FIG. 1. Address buffer AB for receiving address signals Ao to Am and sending complementary address signals to decoder DCR
, the output terminals of the peripheral circuits of the internal control circuit C0NT and the input/output control circuit I10% are concentrated on one side. This takes into consideration the ease of wiring within the IC chip. The internal control circuit C0NT receives the chip enable signal CE and the control signal roll signal and generates an internal clock signal necessary for controlling the data line, word line, etc. Here, the technology enable signal CE is a selection signal for selecting whether or not to operate this SRAM. Memory array M-ARYI,
The word lines in M-ARY2 are driven by word line drive circuits WDI and WD2 that operate based on the output of decoder DCH. Although not particularly limited, the input signal Dinl
~Din36 simultaneous write and output signal Do u t
1 to Dout36 can be read simultaneously.

FIG. 3 shows a circuit diagram of an embodiment of an SRAM to which the present invention is applied. Although not particularly limited, the RAM shown in the figure is formed on a single semiconductor substrate IC chip made of single crystal silicon by the well-known 0MO8 (complementary ff1M08) integrated circuit technology.

Each MO8FET is manufactured by a so-called cell 7 alignment technique using a gate electrode made of polysilicon as a mask for introducing impurities.

The MOSFET constituting the memory cell is of an N-channel type and is formed on a P-type well region formed on an N-type semiconductor substrate. P channel MO8FET is Nff
1 formed on a semiconductor substrate. N channel shop MO8F
The Pa well region as the substrate gate of the ET is coupled to the ground terminal of the circuit, and the NW semiconductor substrate as the common substrate gate of the P-channel type MO8FET is coupled to the power supply terminal of the circuit. Note that the MOSF constituting the memory cell
The configuration in which the ET is formed in the well region is effective in preventing erroneous inversion of stored information in the memory cell caused by α rays or the like.

The memory array M-ARY includes a plurality of memory cells MC1 arranged in a matrix, which is illustrated as a representative example.
Word lines WO, Wl to Wn made of polysilicon layer
and complementary data lines Do, DO.

Each of the memory cells Me has the same configuration as each other,
One specific circuit is shown as a representative of a memory MO8FET QI, Q2 with its gate and drain cross-wired together and its source coupled to circuit ground.
and high resistance R1, R2 made of a polysilicon layer provided between the drains of the MO8FETs QI, Q2 and the power supply terminal VCC. Then, the common connection point of MO8FETQI, Q2 and the complementary data line D
Transmission gates MO8FETQ3 and Q4 are provided between O and Do. Transmission of memory cells arranged in the same row) MO8FETQ3. gates 11 such as Q4 and corresponding word lines WO, Wl and W, respectively shown by way of example.
The input/output terminals of the memory cells arranged in the same column and commonly connected to the terminals 1 and 2 are connected to a corresponding pair of complementary data lines (bit lines or digits It) Do
Connected to tDO.

In the memory cell, MO8FETs QI and Q2 and resistors R1 and R2 constitute a -m flip-flop circuit, but the operating point in the information retention state is quite different from that of a flip-flop circuit in the ordinary sense. That is, in the memory cell MC, in order to reduce power consumption, the resistor R1 maintains the gate voltage of MO8FETQ2 at a voltage slightly higher than its threshold voltage when MO8FETQI is turned off. It is made to have a significantly high resistance value.

Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistors R1 and R2 are MO8FETQI.

The resistance is made high enough to compensate for the drain leakage current of Q2. The resistors R1 and R2 have enough current supply capability to prevent information charges accumulated in the gate capacitance (not shown) of the MO8FET Q2 from being discharged.

According to this embodiment, although the RAM is manufactured by OMO8-IC technology, the memory cell MC is composed of an N-channel MO8FET and a polysilicon resistance element as described above.

In the memory cell and memory array of this embodiment, a P-channel MO8FE'l is used instead of the polysilicon resistance element.
Its size can be made smaller compared to when it is used. That is, when using a polysilicon resistor, the driving MO8FET
It can be formed stacked with the gate electrode of QI or Q2, and its size can be reduced. Then, as when using a P-channel MO8FET, the driving MO
Since it is not necessary to separate it from 8FETQI and Q2 by a relatively large distance, no wasted blank space is generated.

In the figure, the following address selection circuits are used for words iwo, wt to Wn to create an all-unselected state. In this embodiment, an address selection circuit AIC' receiving an address signal AO is used to create a non-selected state for all word lines. That is, the address signal AO is supplied to the input terminal of a C'MOS inverter circuit consisting of a P-channel MO8FETQI2 and an N-channel MO8FETQ13. The output signal of this CMOS inverter circuit (Q12, Q13) is the P channel M
It is input to a CMOS inverter circuit consisting of an O8FETQ14 and an N-channel MO8FETQ15. The output signals of the above two CMOS i/part circuits are CM
It is supplied to OS inverter circuits N3 and N2, and a non-inverted internal address signal aO and an inverted internal address signal aO are output from their respective output terminals.

The non-inverted address signal aO and the inverted address signal a
In order to set both the complementary address signals consisting of
Unlike the S inverter circuits N2, N3, etc., the control signal D
An output signal of a CMOS inverter circuit Nl receiving UM is supplied. That is, the N-channel MO8FETQ1 acts as a source electrode in normal operating conditions.
The electrodes 3 and Q15 are supplied with a high level signal dum such as a power supply voltage VCC formed by a CMOS inverter circuit NIK receiving the control signal DUM or a low level signal dum such as the ground potential of the circuit.

The inverted address signal aO obtained from the output of the inverter circuit N2 is supplied to the operating voltage terminal of a CMOS inverter circuit consisting of a P-channel MO8FETQ16 and an N-channel MO8FETQ17. The output terminal of this CMOS inverter circuit is coupled to word line WO. In addition, the non-inverted address signal aO obtained from the output of the inverter circuit N3 is transmitted to the P-channel MO8FETQ.
CM consisting of 18 and N-channel MO8FETQ19
It is supplied to the operating voltage terminal of the OS inverter circuit. The output terminal of this CMOS inverter circuit is coupled to word line W1. One selection signal di formed by an address decoder circuit DCII receiving alternate address signals AI to Am is commonly supplied to the inputs of these CMOS inverter circuits.

The inverter circuit N2. Inverter circuit N4 similar to N3. N
Complementary address signals aO, aO formed by
P-channel MO8FETQ receiving the output signal dl
22 and N-channel MO8FETQ23 and P-channel MO8FETQ20 and N-channel MO8FETQ2
A selection drive circuit consisting of 1, etc. is provided.

A pair of complementary data lines Do, D in the memory array
Although not particularly limited, O is directly coupled to the input terminal of the differential amplifier sense amplifier. That is, the complementary data line DO
, DO are N-channel differential amplifier MO8FETQ7
．． Each is coupled to the gate of Q8. These differential M
The drains of O8FETQ7 and Q8 are connected to P-channel type MO8FETQ9. An active load circuit consisting of QIO is provided. The above differential amplification MO8FETQ7. Q8 is placed between its common source and the ground potential point of the circuit, and is activated by an N-channel power switch M08FETQ11 that is turned on by the sense amplifier operation timing signal SaC. Sense amplifiers similar to those described above are also provided on other complementary data lines (not shown). The amplified output signal of the sense amplifier is controlled by the control I signal.
It is transmitted to the readout circuit RAO which outputs ut. This readout circuit RAO puts its pair of output terminals into a high impedance state or a floating state when in a memory holding state or a convolution state.

Further, an output terminal of a write circuit WAO is coupled to the complementary data lines Do and DO. This write circuit WA
O outputs a complementary data signal corresponding to the write signal D1n to the complementary data lines DO when the operation is controlled by the control signal W and it is in the operating state, in other words, during a write operation. do. The write circuit WAO puts its pair of output terminals into a high impedance state or a floating state when it is in an inactive state, in other words, in a memory holding state or a reading state.

In this embodiment, complementary data lines Do, DO include:
The following precharge circuit is provided. A pair of complementary data iDo and DO is an N-channel MO8F controlled by a precharge signal φp, although it is not particularly limited.
Power supply voltage VCC is supplied via ETQ5 and Q6, respectively. That is, precharge MO8FETQ5. Q
6 is turned on, complementary data lines DO, Do, etc. are precharged to a high level <Vcc-Vth).

Here, Vth is MO8FETQ5. This is the threshold voltage of Q6, etc. Precharge MO8FETs similar to those described above are also provided on other complementary data lines (not shown). Note that the precharge MO8FET is the N-channel MO8FE mentioned above.
TQ5. Instead of Q6 etc., a P-channel MO8FET may be used. In this case, an inverted precharge signal φp may be supplied.

The control circuit C0NTl receives a chip selection signal CE.

In response to the read/write control signal R/W and the output signal dum of the inverter circuit N1, the precharge signal φp, the sense amplifier operation timing signal sac,
A write signal W, a read signal R, an operation timing signal φ of the address decoder DCH, etc. are formed. Note that address buffer AB receives address signals A, -Am and sends out a complementary address signal to decoder DCRK.

Next, an example of the operation of the static RAM will be described with reference to the timing chart shown in FIG. This timing diagram shows a read cycle.

Although not shown, the timing signal φ is set to a low level while the chip selection signal CE is set to a low level. As a result, address decoder DCR sets all outputs to high level and all word lines WO.

Wl, . . . , Wn are set to a low level non-selected state.

Furthermore, when the chip selection signal CE is brought to a high level, the timing signal φ is brought to a high level, and in response to this, the decoder DCR starts operating.

Decoder DCR outputs output signals d1 to dl according to the address complementary signal applied from address buffer AB.
Selectively set one of the output signals to a low level.

By the way, if the chip selection signal CE is kept at a low level for a relatively long period of time, in other words, if the memory retention state is continued for a relatively long period of time, the complementary data &DO will not be processed.

The precharge potential of DO etc. gradually decreases due to its natural discharge.

When accessing the memory after such a relatively long memory retention state, the control signal DU is activated almost in synchronization with the rise of the chip selection signal CE to a high level.
Set M to low level. As a result, the output signal dum of the inverter circuit N1 is set to a high level, so if the address signal AO is at a high level, the first stage circuit receiving it will output the output signal dun of the inverter circuit N1 via its N-channel MO8FETQIa. A high level is passed to its output node. Since the high level of this output node turns on the N-channel MO8FETQ15 of the next stage circuit, the high level of the output signal dum also brings the output node to the high level. Also,
When the address signal AO is at a low level, its output node is set at a high level via the P-channel MO8FETQ12 of the first stage circuit. Since the high level of this output node turns on the N-channel MO3FET QI 5 of the next stage circuit, the high level of the signal dun also brings the output node to the high level. As a result, inverter circuit N2. The output signal of N3, in other words,
Internal complementary address signal aO,a.

are set to a low non-selection level in accordance with the low level of the control signal DUM, regardless of the level of the address signal AO.

Therefore, since no operating voltage is supplied to the CMOS inverter circuit for driving word lines, all word lines WO
to Wn are set to a low non-selection level.

The control circuit C0NTl forms a high-level precharge signal φp in accordance with the high level of the internal control signal dum. As a result, the complementary data line Do is naturally discharged due to the leakage current.

Dθ and the like are precharged to the above-mentioned high level.

In parallel with the above precharge operation, in other words, the address decoder circuit DC is activated by the operation timing signal φ generated by the high level of the chip selection signal CE.
R is the address signal AI or Am input at that time.
is decoded, and after the operation time Td, for example, one selection signal d1 is set to low level. Before the operating time Td required for decoding these address signals AI to Am has elapsed, the control signal DUM is set to a high level.

As a result, two CMOs receiving the address signal AO
Since the S inverter circuit is given the low level of the internal signal dun, the internal complementary address signals aO, aO are
It is set to high level and low level according to the level of the address signal AO. When the address signal AO is at a high level, the non-inverted internal address signal aO is set at a high level, and the P-channel MO is turned on by the low level of the output signal d1 of the address decoder circuit DCH.
The word line Wl is set to a high selection level through the 8FET QI8. In addition, the word line w.

is P due to the low level of the decoded output signal d1.
Channel MO8FETQ16 is turned on, but
The low level of the inverted internal address signal aO maintains the low non-selection level.

As is clear from the embodiments described above, according to the present invention, the precharge operation of the data lines DO, DO is performed in parallel with the address signal decoding operation by the decoder DCH. Therefore, data! ! There is no need to provide a dedicated period for precharging Do and DO. In particular, according to the above embodiment, immediately before the output signal di of the decoder DCR is formed,
Precharge operation ends. Therefore, the memory access time from when the chip selection signal CE is set to high level until the output data Dout is sent out is not extended by the precharge operation.

Note that even if the operating time of the decoder DCH is as short as Td', malfunctions such as destruction of memory cell information do not occur. At least during the period when precharge signal φp is at high level, internal address signal a is
This is because o and io are both set to low level.

In the above embodiment, the control signal DUMt-8RAM is supplied from outside, but the control signal is not limited to this, and may be formed by an internal circuit that receives the chip selection signal CE. especially,
In the case of an IC chip dedicated to SRAM, there may be restrictions on the number of bonding pads or the number of external leads of the IC package.

Therefore, in this case, it is sufficient to use the internal circuit within the circle for generating the control signal DUM.

In the waveform diagram of FIG. 4, when the chip selection signal CE is set to a low level, an l switch precharge signal φp is generated in synchronization with this, and the precharge operation of the complementary data lines DO, DO, etc. is performed again. be exposed.

However, according to the present invention, the above-mentioned re-precharge operation can be omitted. This is because it is sufficient if the data lines Do, Do are precharged at the start of the memory cycle.

The waveform diagram in FIG. 4 shows a memory cycle for reading, but when this operation cycle is used as a dummy cycle, the sense amplifier operation timing signal 11Le
etc. will be stopped from occurring. In this case, the dummy cycle period can be set short. Further, even if the potential of the data &lDO, Do before entering the dummy cycle is at a low level due to natural discharge, the information stored in the memory cell will not be destroyed as described above.

FIG. 5 shows another embodiment of a circuit which sets both internal complementary address signals to a non-select level. Two cascade-type inverter circuits N6 receiving address signal AO. NOR gate circuits Gl and G2 are provided at the output of N7, and the internal dummy cycle control signal dum is supplied to their control terminals. Further, the word line drive circuit includes an AND gate circuit G3.
G4 may be used.

In addition, the memory cell as a static type RAM is P
A static type clip 70 tube circuit configured by combining a channel MO8FET and an N-channel MO8FET may be used. Further, a column selection circuit may be provided in the complementary data lines to select a pair of complementary data lines from among a plurality of complementary data lines and couple them to a sense amplifier or a write circuit.

The memory cell is also a so-called mask ROM (read read memory), which is a memory element that has a threshold voltage higher or lower than the selected level of the word line according to stored information.
only memory) or EFROM (electronic memory)
(program ROM). In such a ROM, when a data line is precharged to obtain a readout signal, a similar address selection circuit is used to achieve low power consumption and high-speed readout.

FIG. 6 is a circuit diagram showing another embodiment of an SRAM to which the present invention is applied. The main differences from the SRAM shown in FIG. 3 are the values of the precharge voltages of the data lines Do and Do and the configuration of the precharge circuit. SRA shown in Figure 6
M has a precharge circuit PC and a harp precharge circuit HPC for precharging to a voltage 1/2 of the data line pair power supply voltage VCC. The precharge circuit pc connects each data line pair (Do, Do), (D 1
．． P-channel type MO8FE for supplying power supply voltage VCC to one data line DO, °D・1 of DI)
N-channel MO for supplying circuit ground voltage GND to TQ36°G38 and the other data lines Do and DI.
8FETQ37. MO8FETQ37. including G39.
The gate of G39 and the gate of MO8FETQ36゜G38 are supplied with signals φp1゜φp1 of opposite phases, respectively, so that one data line Do, DI is charged with a high-level voltage that is almost equal to the power supply voltage VCC. The other data lines Do and Di are precharged with a four-level voltage approximately equal to the ground voltage GND. The half precharge circuit RPC connects each data line pair (DO, Do)
.

MOSFET pair (G40.G41) for shorting between a pair of data lines for (DI, DI).

(G42.G43). Each MOSFET pair consists of a P-channel MO8FET and an N-channel MO8FET, and forms a switching circuit in response to gate signals φp2°φp2 of opposite phase. After the data line pair (DO2Do), (DI, DI) is precharged to the above level by the precharge circuit PC, each data @DO,D is operated by operating the half precharge circuit RPC.
o.

DI, DI, will be precharged to a voltage approximately 1/2 of the power supply voltage VCC. By setting the precharge level to 1/2 VCC, the memory cell MC
It is possible to speed up the operation when reading information.

This is because the width of the voltage change on the data line that occurs when reading information is limited to 1/2 of the power supply voltage Vcc.

Memory cell MC is a pair of complementary MO8FETs (G30, G32) forming a flip-flop circuit.

(G31.G33) and MO8FET G34 for transmission,
G35. By constructing the 7-rip, 70-tube circuit using complementary WMO8FETs, the power consumption of the memory cell MC can be reduced. Memory cells MC are arranged in a matrix, and a mesori array M
- Configure ARY. 1 in memory array M-ARY
To select one row, the word, Hw, corresponds to each row.
o.

Wl, . . . are provided. Each word line is connected to each transmission gate MO8FE of memory cells MC arranged in the same row.
Commonly connected to the gates of T. A word line driver WD is provided to selectively drive either word line WO or Wl to a high level. word iw
Complementary MO8FET (Q72.Q7
3) and a complementary amount MO8F for driving the word line Wl.
ET (Q74.Q75) are complementary MO8FETs (Q16jQ17) and (Q18°Q1
It has the same configuration as 9). Although not shown in the embodiment of FIG. 6, a circuit similar to the address input circuit AIC shown in FIG. 3 is provided. MO8FETQ76 and Q77 provided in the word line driver WD each receive an internal address signal aO.

By receiving aO at the gate, one of the word lines WO and Wl is forcibly fixed to a low level.

The decoder DCR performs a precharge operation or a discharge operation on its output line (dl) using a timing signal φ.
MO8FET Q68 and Q71 to control according to
and the above output based on the output signal of address buffer AB! M for selectively discharging (di)
Timing signal φ including O8EETQ69 and Q70
By changing from low level to high level, M0
SFETQ68 transitions to the OFF state, and MO8FETQ71 transitions to the ON state. As a result, decoder DCR operates according to the output signal of address buffer AB at that time.
After a predetermined period, the level of the output signal d1 is determined.

One sense amplifier SA for amplifying signals appearing on the data line pairs is provided for every two data line pairs. Therefore, a data line selection circuit DS is provided to select one data line pair connected to the sense amplifier. That is, each data line DO, Do, DI
, corresponding to DI, MOSFET (Q44.Q45),
(Q46°Q47), (Q48.Q49), (Q50.
Q51) is provided and acts as a switching circuit (internal address signals (ai, ai) are used as control signals for this switching circuit.The sense amplifier SA is
Differential increase in N channel amount @MOS FETQ55. Q
56 and these differential MO8FETQ55. P-channel type MO configured as a current mirror to the drain of Q56
8FETQ53. An active load circuit consisting of Q54 is provided. The above differential amplification MO8FETQ55. Q56
is an N-channel power switch MO8 provided between its common source and the ground potential point of the circuit and turned on by the sense amplifier operation timing signal aae.
It is activated by FETQ57.

Note that the P-channel transistor Q52 driven by the timing signal 1ae is connected to the output line of the sense amplifier SA when the timing signal M is at a low level. This is provided to prevent S from being in a 70-ting state.

The output circuit DC includes a MOSFET (Q62°Q63) for capturing the output signal of the sense amplifier via an inverter N8 in synchronization with the timing signal φR9φR, and an inverter N9 forming a latch circuit for holding this captured signal. ．． NIO and timing signal φ0. MO8FETQ64.COM constitutes an output buffer for sending an output signal Dout to the outside of the SRAM in synchronization with φO. Q
65. The write circuit WC including Q66 and Q67 outputs a write signal din' in synchronization with the timing signals φW and φW.
1. MO8FETQ58゜Q to take in dial
59. Q60. Including Q61. Control circuit C0N
T2 receives a chip enable signal CE and a read/V input signal OE applied from outside the SRAM.
Each strain forms internal control signals.

FIG. 7 is an operational waveform diagram of the SRAM shown in FIG. 6.

Period T1 represents a write cycle, and periods T2 to T4 represent a read cycle. Period T3 indicates a state in which neither reading nor writing is performed, that is, a wait period. Period TI, T2
and T4 are memory cycles, and the basic operations are the same, so the read cycle of period T2 will be explained.

Address signal A for specifying one or more memory cells MC in which information to be read is stored.

~Am is supplied to address buffer AB. Also, to specify that it is a read cycle, read/write
When the write control signal R/W is set to high level and the chip enable signal CE is set to high level, the timing signal φ is set to high level in synchronization with this, and the decoder DCR starts operating. Until the operation of decoder DCH is completed, the potential of its output line d1 maintains the no level.

Output i! i15! This is because the potential of di is precharged to a high level. While the control signal DUM is at a low level, both internal address signals aO and ao are at a low level. Therefore, words iWo and Wl are both fixed at low level regardless of the output of decoder DCH. Note that if the internal address signals ao and aO are unconditionally set to a low level in response to the fall of the control signal DUM to a low level, a malfunction may occur. Memory cell M
If the control signal DUM is erroneously set to low level while the information of C is being transmitted to the data line pair, all word lines will be set to low level and no information will be transmitted to the data line pair thereafter. It is. Therefore, when the control signal DUM is set to a low level, if the chip enable signal CE is at a low level, the internal address signals ao, , aO are set to a low level, and if the chip enable signal CE is at a high level, the internal address signals ao, +aO are set to a low level. address signal A
It is controlled so as to maintain the complementary signal level according to O.

In synchronization with the fall of the control signal DUM to low level,
Timing signal φp1 rises. As a result, data line D
O is precharged to high level, and data line DO is set to low level. After that, the half precharge circuit HPC is activated by the rise of the timing signal φp2, and both data &DO2DO are 1/2 of the power supply voltage VCC.
is precharged to the voltage of

In parallel with the above precharge operation, in other words, the address decoder circuit DC is activated by the operation timing signal φ generated by the high level of the chip selection signal CE.
R decodes the address signal input at that time and sets, for example, one selection signal d1 to a low level after the operation time Td.

Before the operating time Td required for decoding these address signals AI to Am has elapsed, the control signal DUM is set to a high level. As a result, internal complementary address signal a
o and io are set to high and low levels according to the level of address signal AO. When the address signal AO is at a high level, the non-inverted internal address signal aO is set at a high level, and the word line Wl is set at a high level through the P-channel MO8FETQ74, which is turned on by the low level of the output signal di of the address decoder circuit DCH. be brought to a selective level. Note that the P-channel MO8FET Q73 of the word line WO is turned on by the high level of the decoded output signal d1, but is maintained at the low non-selection level by the low level of the inverted internal address signal aO.

As is clear from the embodiments described above, according to the present invention, the precharge operation of the data lines DO, Do is performed in parallel with the address signal decoding operation by the decoder DCH. Therefore, data lines DO, D.

There is no need to set up a dedicated period for precharging. In particular, according to the above embodiment, the precharge operation ends immediately before the output signal di of the decoder DCR is formed. Therefore, the memory access time from when the chip selection signal CE is set to high level until the output data Dout is sent out is not extended by the precharge operation.

If the wait period T3 after the read cycle is long, the potential of the data iDO, Do becomes an unstable potential Vd due to leakage current or the like. However, according to this invention, the period T
In the read cycle No. 4, data lines DO and DO are first read.
Since the precharge operation is performed, the wait period T
There is no problem even if 3 is long.

Note that even if the operating time of the decoder DCH is short, malfunctions such as destruction of memory cell information do not occur. This is because, at least during the period when precharge signal φp1 or φp2 is at high level, internal address signals io and aO are both at low level according to control 111 signal DUM.

In the above embodiment, the control signal DUM is supplied from outside the SRAM, but the chip selection signal C
It may be formed by an internal circuit that receives E. In particular, S
In the case of an IC chip dedicated to RAM, there may be restrictions on the number of bonding pads or the number of external leads of the IC package.

Therefore, in this case, an internal circuit for generating the control signal DUM may be provided.

〔effect〕

According to the above embodiment according to the present invention, the following effects can be obtained.

(1) Without setting a pre-charge period for each percentage,
Since the memory cells can be accessed, the memory cycle can be shortened, or in other words, the operation speed can be increased.

(2) All word lines can be brought into a non-selected state by a simple configuration in which complementary address signals of one or more specific bits are both applied to a non-selecting level.

(3) With a simple configuration in which a voltage at a level according to the control signal is supplied to one operating voltage terminal of a cascade-type CMOS inverter circuit that receives an address signal,
Both internal complementary address signals can be at the same level. This makes it possible to create a non-selected state for all memory cells.

In the above explanation, the invention made by the inventor of the present application has been mainly explained using as an example the case where it is applied to a static RAM built in a digital integrated circuit, which is the technical field that is the background of the invention, but the present invention is not limited to this. It can also be used, for example, in a static RAM built into an l-chip microconverter, a ROM read by precharge/discharge, or a similar semiconductor storage device as an external storage device.

[Brief explanation of drawings]

FIG. 1 is a plan view of an IC chip to which an SRAM to which the present invention is applied has an inner wing, FIG. 2 is a layout diagram of the above-mentioned SRAM, and FIG. 3 is an example of an SRAM to which the present invention is applied. FIG. 4 is a timing diagram showing the operation of the circuit shown in FIG. 3; FIG. 5 is a circuit diagram showing another embodiment of a part of the circuit shown in FIG. 3; FIG. 7 is a circuit diagram showing another embodiment of the SRAM to which the present invention is applied. FIG. 7 is a timing diagram showing the operation of the circuit shown in FIG. 6. Engineering 10 buffer...Input/output buffer 7 buffer, BP...Wire bonding pad, EU...Arithmetic circuit section, Engineering U
...instruction, memory access control unit, OU...operand control unit, SU...interrupt control unit, QU...microinstruction, scan control unit, M-ARY, M-ARYl
, 2...Memory array, DCR...Address decoder, WD, WDI, 2...Word line drive circuit, AB/
C0NT...address buffer/internal control circuit, MC
...Memory cell, AIC...Address input circuit, W
AO: Commitment circuit, RAO: Readout circuit, O
C...Output circuit, DS...Data line selection circuit, PC
...Precharge circuit, RPC... Half precharge circuit, Ilo... Input/output control circuit, SA...
sense amplifier. Agent Patent Attorney Katsuo Ogawa' Figure 1 sp ap Figure 2 j! 'f5 Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] 1. A plurality of memory cells each provided at the intersection of a data line and a plurality of word lines, a charge circuit for applying a predetermined potential to the data line in synchronization with a timing signal, and a semiconductor. a selection circuit for selecting a predetermined word line from the plurality of word lines in synchronization with a selection signal for selecting a memory, and an operation period of the charge circuit and an operation period of the selection circuit are at least the same. 1. A semiconductor memory characterized in that parts of the semiconductor memory overlap each other. 2. The semiconductor memory according to claim 1, wherein the data line is a static type RAM constituted by a pair of data lines. 3. The semiconductor memory according to claim 2, wherein the selection circuit includes a decoder for decoding the address signal. 4. The semiconductor memory according to claim 3, further comprising a word line drive circuit having means for setting the potentials of the plurality of word lines to a non-select level during operation of the charge circuit. 5. The semiconductor memory according to claim 4, wherein the charge circuit has means for setting the potential of the pair of data lines to 1/2 of the power supply voltage. 6. includes an address input circuit having means for setting complementary address signals formed from one address signal to a non-select level; 5. The semiconductor memory according to claim 4, wherein a word line drive circuit is controlled.