JP3770565B2 - Semiconductor device - Google Patents

Description

[0001]
[Field of the Invention]
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of reducing power consumption and capable of burn-in for word line batch selection.
[0002]
[Prior art]
A word line driver constituting a semiconductor memory device can apply a CMOS inverter to a circuit for selecting a word line. The CMOS inverter is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in series between the drains, and the resistance between the source and drain of the P-channel MOS transistor is increased in order to increase the input / output operation speed. Even when the CMOS inverter is not operating, the leakage current between the power source and the GND is allowed. As a technique for minimizing the leakage current of the CMOS inverter, a switch is provided between the CMOS inverter and its power supply potential, the switch is turned on during the operation period of the CMOS inverter, and the power supply potential is supplied. There is a low-leakage switch that is turned off during a non-operation period to turn off the power supply potential.
[0003]
[Problems to be solved by the invention]
The low-leakage switch is merely a circuit for reducing the leakage current of the CMOS inverter. The CMOS inverter is used as a switch for selecting a word line in a semiconductor memory device. Since the output of the CMOS inverter is supplied to the word line, the present inventors have found that it is effective to add a circuit for supplying a burn-in potential targeting the gate of the word line to the low-leakage switch. It was.
[0004]
An object of the present invention is to provide a technique for combining a low leakage circuit of a CMOS circuit and a burn-in potential supply circuit in a semiconductor memory device including a word line driver formed of a CMOS circuit.
[0005]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0006]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0007]
That is, in a semiconductor memory device having a memory cell array in which selection terminals of a plurality of memory cells arranged in a matrix are coupled to a word line and a data terminal is coupled to a bit line, the address signal is decoded to select the word line An address decoder for forming a signal, a word line driver comprising a CMOS circuit provided corresponding to each word line for driving the word line to a selection level in accordance with a word line selection signal of the address decoder, In a state where a word line is selected by a word line selection signal and a switching element arranged in a path for supplying operation power to the word line driver, the switching element is turned on, and wafer burn-in (semiconductor chip completed in a wafer state) In the state where burn-in with burn-in current is A control circuit for controlling the switch elements to be always on, and an all word line selection circuit for forcing all word line selection signals supplied to the word line driver to a selection level in response to a wafer burn-in instruction. A semiconductor memory device is configured. In a semiconductor memory device having a memory cell array in which selection terminals of a plurality of memory cells arranged in a matrix are coupled to a sub word line of a hierarchical word line system and a data terminal is coupled to a bit line, a first address A first address decoder for decoding a signal to form a main word line selection signal; a main word line driver for driving the main word line to a selection level according to the main word line selection signal; and a second address signal for decoding And a second address decoder for forming a sub word line selection signal, and provided corresponding to each sub word line for driving the sub word line to a selection level according to the main word line selection signal and the sub word line selection signal. The sub word line driver composed of a CMOS circuit and each of the above sub word line drivers. In a state where the switch element arranged in the power supply path, and the sub word line is selected by the main word line selection signal and the sub word line selection signal, the switch element is turned on and the wafer burn-in is instructed. Then, a control circuit for controlling the switch elements to be always on, an all sub word line selection circuit for forcing all sub word line selection signals supplied to the sub word line drivers to a selection level in response to a wafer burn-in instruction, and a wafer A semiconductor memory device is configured with all main word line selection circuits for forcing all main word line selection signals supplied to the main word line driver to a selection level in response to a burn-in instruction. A second switch element disposed in a path for supplying operating power to each of the main word line drivers, and the second switch element in an on state when the main word line is selected by a main word line selection signal And a control circuit for controlling the second switch element to be always on in a state where wafer burn-in is instructed. The memory cell can be a dynamic memory cell composed of a selection transistor and a storage capacitor.
[0008]
[Action]
According to the above means, the selection potential of the word line is supplied to the word line driver via the switch. The switch is turned on when the word line is selected, and the selection potential is supplied to the CMOS inverter constituting the word line driver and is supplied to the selected word line. The switch also performs supply control of the potential for wafer burn-in targeting the gate of the memory cell. The switch is turned on during wafer burn-in, and the potential for wafer burn-in is applied to all word lines selected by all word line selection circuits. Supply. Further, in a hierarchical word type semiconductor memory device, the selection potential supplied to the sub word line is not always supplied to the sub word line driver, but via the switch that is turned on when the sub word line is selected. The voltage is supplied to the CMOS inverter that performs selection, and is supplied to the selected sub-word line. The switch also controls supply of a wafer burn-in potential targeting the gate of the memory cell, and is turned on at the time of wafer burn-in, and the wafer burn-in potential is applied to all sub-word lines selected by all sub-word line selection circuits. Supply. In the hierarchical word type semiconductor memory device, if the second switch is provided in the main word line driver, the selection potential supplied to the main word line is not always supplied to the main word line driver. It is supplied to a circuit that selects a main word line via a second switch that is turned on when a line is selected, and can be supplied to the selected main word line. The memory cell can be composed of a 1-transistor, 3-transistor, and 4-transistor dynamic memory cell.
[0009]
【Example】
FIG. 2 is a block diagram showing an example of a DRAM (dynamic random access memory) which is a semiconductor memory device of the present invention. According to the figure, the DRAM 200 includes a memory cell array 201 composed of, for example, a one-transistor dynamic memory cell including a selection transistor and a capacitor, and a row for selecting a word line by decoding a row address signal XADR. An address decoder (X decoder) 202, a word line driver 203 that drives the selected word line by supplying a selection potential, and a column address that decodes the column address signal YADR and selects a column selection signal that specifies a data line A decoder (Y decoder) 204, a column switch circuit 205 that selects a data line using the selected column selection signal, and amplifies the potential supplied to the data line from the memory cell selected by the word line and the data line. Sense amplifier 206 and memory access And a control circuit 207 supplies the use of various control signals. The read / write data is input / output to / from the column switch circuit 205 via the input / output terminals Do / Di. The word line driver 203 uses a CMOS inverter as a word line selection circuit, and can supply a wafer burn-in potential VBI as a power supply potential from, for example, a bonding pad BP1. The word line driver 203 is supplied with a wafer burn-in mode signal BI for setting the wafer burn-in mode from the bonding pad BP2. The DRAM 200 is in a wafer burn-in mode when the wafer burn-in mode signal BI is at a high level, and is in a memory access mode when it is at a low level. The semiconductor memory device 200 has various outputs from a control circuit 207 to which a row address strobe signal RAS * (hereinafter, * means a row enable signal), a column address strobe signal CAS *, a write instruction signal WE *, and the like are supplied. A memory access operation is executed according to the control signal.
[0010]
An example circuit diagram of the word line driver 203 is shown in FIG. As shown in the figure, the word line driver 203 includes a selection circuit 102 including a CMOS inverter provided corresponding to each row address decode signal X0 * to Xn * supplied from the row address decoder 202, and a row address. The switch 101 is turned on / off by a strobe signal RAS * and a wafer burn-in mode signal BI, and an all word line selection circuit 103 that receives the wafer burn-in mode signal BI and row address decode signals X0 * to Xn *. The The power supply potential supplied to the switch 101 is the selection potential VPP supplied in the memory access operation or the wafer burn-in potential VBI supplied from the bonding pad BP1 at the time of wafer burn-in. The selection circuit 102 is composed of a CMOS inverter in which a P-channel MOS transistor Qp and an N-channel MOS transistor Qn are connected in series at both drains. The source of the P-channel MOS transistor Qp is connected to a power supply terminal capable of supplying the selection potential VPP or the wafer burn-in potential VBI via the switch 101, and the source of the N-channel MOS transistor Qn is connected to GND. Corresponds to one word line WLn. The switch 101 is composed of, for example, a P-channel MOS transistor, and a switch control signal φ1 that is output via an inverter as an output of a NAND circuit having two inputs of a row address strobe signal RAS * and an inverted signal of the wafer burn-in mode signal BI. * Is supplied to the gate and controlled. The all word line selection circuit 103 is composed of an AND circuit having two inputs of each row address decode signal X0 * to Xn * and an inverted signal of the wafer burn-in mode signal BI.
[0011]
When performing normal memory access, the wafer burn-in signal BI is set to the low level, and the switch 101 is turned on only when the row address strobe signal RAS * is enabled. Since the wafer burn-in mode signal BI is inverted and supplied to the AND circuits constituting all the word line selection circuits 103, the output of the AND circuit in which the row address decode signals X0 * to Xn * are enabled Only outputs a low level, and one word line WLn is selected. The resistance value between the source and drain of the switch 101 in the off state is set to be larger than the resistance value between the source and drain of the P channel type MOS transistor Qp of the MOS circuit 102 in the off state. Therefore, the leakage current of the CMOS inverter can be reduced by the switch 101 as compared with the CMOS inverter without the switch 101. In the wafer burn-in mode, the wafer burn-in mode signal BI is set to the high level, and the switch 101 is turned on. At this time, the wafer burn-in mode signal BI is inverted and supplied to the all word line selection circuit 103, and all the word lines WL0 to WLn are selected. At this time, by supplying wafer burn-in voltage VBI from bonding pad BP1, wafer burn-in potential VBI is simultaneously applied to the gates of all memory cells.
[0012]
FIG. 3A shows a time chart of the word line selection operation in the word line driver 203. According to FIG. 5A, the selection of the word line WLn is enabled in synchronization with the low edge of the row address strobe signal RAS *, and the switch control signal φ1 * is enabled, and the selection potential VPP is supplied to the selection circuit 102. To be done. The selection potential VPP is supplied to the word line WLn which is enabled and selected by the decode signal Xn * supplied from the X decoder 202. When the memory access is completed, the row address strobe signal RAS * is set to the high level, the decode signal Xn * selected along with it is disabled, and the selected word line WLn is not selected. Finally, the switch control signal φ1 * is disabled, and supply of the selection potential VPP of the word line WLn to the selection circuit 102 is suppressed. As described above, the supply of the selection potential VPP of the word line WLn to the CMOS inverter constituting the selection circuit 102 is not always performed, but is performed only while the selection operation of the word line WLn is performed. When the conventional selection of the word line WLn is performed by a CMOS inverter, since the switch 101 is not provided, the selection potential VPP of the word line WLn is always supplied to the CMOS inverter. Since the on-resistance between the source and drain of the P-channel MOS transistor Qp constituting this CMOS inverter is set to a small value in order to increase the selection speed, a leakage current is generated between the source and drain. ing. If the switch 101 is provided as in the word line driver 203 of this embodiment, the selection potential VPP is supplied to the CMOS inverter when the switch control signal φ1 * is enabled, that is, the selection operation of the word line WLn. Can be limited sometimes. Thus, it is possible to suppress an undesired leak current of the CMOS inverter and to reduce power consumption.
[0013]
FIG. 3B shows a time chart in the wafer burn-in mode in the word line driver 203. According to FIG. 5B, at the time of wafer burn-in, the low address strobe signal RAS * is set to high level, and the wafer burn-in mode signal BI is set to high level, so that the switch control signal φ1 * is fixed at low level. Is done. At this time, a wafer burn-in potential VBI is supplied from the bonding pad BP1 to the CMOS inverter instead of the selection potential VPP. Since all the word lines WL0 to WLn are collectively selected by the wafer burn-in mode signal BI, wafer burn-in can be performed on the gates of all the memory cells.
[0014]
FIG. 4 is a block diagram showing another example of a DRAM which is a semiconductor memory device of the present invention. According to the figure, the DRAM 400 employs a hierarchical word line system for the DRAM 200. In the hierarchical word system, the word lines are divided into main word lines and sub-word lines in order to alleviate the high density arrangement of the word lines, and are arranged so as to partially avoid the high density arrangement. A main word line and a sub word line are selected by a row address signal used in the hierarchical word system, and a memory cell row to be accessed is designated. The DRAM 400 replaces the word line driver 203 of the DRAM 200 with a sub word line driver 402 that selects a sub word line connected to a selection terminal of a memory cell, and a main word line driver 401 that selects a sub word line in units of the sub word line driver 402. Is provided. Accordingly, in the DRAM 400, the decoder of the row address signal XADR, for example, the XM decoder 404 that selects the main word line using the upper bits of the row address signal XADR, and the sub word line using the lower bits of the row address signal XADR. An XS decoder 405 for selection. In the hierarchical word system, a plurality of sub word line drivers 402 are provided corresponding to the main word line, and the sub word line driver 402 is supplied with an FX for supplying a selection potential to the sub word lines in accordance with a decode signal supplied from the XS decoder 405. A driver 406 is connected. The FX driver 406 has a circuit configuration including the switch 101 and the selection circuit 102 of the word line driver 203, and the output of the CMOS inverter is supplied to the sub word line. Also, a bonding pad BP1 for supplying a wafer burn-in potential VBI to the sub word line is provided, and the wafer burn-in potential VBI is supplied to the FX driver 406. The DRAM 400 has a memory access mode and a wafer burn-in mode, and a wafer burn-in mode signal BI can be supplied to the main word line driver 401 and the FX driver 406 from the bonding pad BP2. When the wafer burn-in mode signal BI is set to the high level and the wafer burn-in mode is instructed, the main word line driver 401 selects all the main word lines, and the FX driver 406 selects all the sub word lines. Put into state.
[0015]
FIG. 5 shows an example of a connection configuration of the main word line driver 401, the FX driver 406, and the sub word line driver 402. The main word line driver 401 outputs the outputs of the NOR circuit 501 and the NOR circuit 501 having two inputs of the wafer burn-in mode signal BI and the main word line decode signal XM0 supplied from the XM decoder 404, and the gate of the P-channel transistor. The CMOS inverter A received in common at the gates of the N-channel transistors is configured as a basic unit. The output of the CMOS inverter A is supplied to the main word line MWL0 (in FIG. 5, the basic unit corresponding to the main word line MWL0 is shown). The switch 101 is provided between the CMOS inverter A and its power supply potential. One main word line MWLn is selected by the basic unit, and a plurality of sub word line drivers 402 corresponding to the main word line MWLn can be selected. The FX driver 406 basically includes a NOR circuit 502 having two inputs of the wafer burn-in mode signal BI and the sub word line decode signal XS0 supplied from the XS decoder 405, and a CMOS inverter B receiving the output of the NOR circuit 502 at the gate. Configured as a unit. The output of the CMOS inverter B is supplied to the sub word line SWL0. The switch 101 is provided between the CMOS inverter B and its power supply potential. One sub word line SWLi is selected by the basic unit. When the wafer burn-in mode signal BI is enabled (high level), the outputs of the CMOS inverters A and B are connected to GND. The basic units corresponding to the other main word lines MWLn have the same circuit configuration.
[0016]
In the sub word line driver 402, for example, a structural unit composed of a CMOS inverter C composed of a P channel type MOS transistor and an N channel type MOS transistor and an N channel type MOS transistor T corresponds to one sub word line SWLi. In the figure, a structural unit corresponding to the sub word line SWL0 is shown. The main word line MWL0 is inverted and connected to the gate of the P-channel transistor and the gate of the N-channel transistor constituting the CMOS inverter C by the inverter. The main word line MWL0 is connected to the gate of the N-channel MOS transistor T. The output FX0 of the FX driver is connected to the source of the P-channel transistor and the drain of the N-channel transistor T of the CMOS inverter C. The source of the N-channel transistor T is connected to the output of the CMOS inverter C and connected to the sub word line SWL0. Other structural units have the same circuit configuration.
[0017]
During a normal memory access operation, the power supply potential of the CMOS inverters A and B is set to the selection potential VPP, and the selection potential VPP is supplied to the selected main word line MWL0 and the selected sub word line SWL0 only during memory access. . At the time of wafer burn-in, the wafer burn-in potential VBI is set to the power supply potential of the CMOS inverter B via the bonding pad BP1. When the wafer burn-in mode signal BI is enabled, all the main word line drivers 401 and all the FX drivers 406 are driven, and the wafer burn-in potential VBI is applied to all the sub-word lines SWL0 to SWLi selected at once. Supplied at the same time.
[0018]
According to the said Example, the following effects can be obtained.
(1) In the DRAM 200, the supply of the selection potential VPP supplied to the word line driver 203 is controlled by the switch 101 that is turned on in synchronization with the enable state of the row address strobe signal RAS * in the memory access mode. In the wafer burn-in mode, the switch 101 is always turned on regardless of the state of the row address strobe signal RAS *, and the wafer burn-in potential VBI is simultaneously supplied to all the word lines WL0 to WLn via the bonding pad BP1. By using the switch 101, the leakage current of the CMOS inverter constituting the word line driver 203 can be reduced.
(2) In the DRAM 400, the selection potential VPP supplied to the main word line driver 401 and the sub word line driver 402 is supplied by the switch 101 that is turned on in synchronization with the enable state of the row address strobe signal RAS * in the normal mode. Is controlled. In the wafer burn-in mode, the switch 101 of the main word line driver 401 is always turned on regardless of the state of the row address strobe signal RAS *, and the selection potential VPP is supplied to all the main word lines MWL0 to MWLn simultaneously. At this time, the switch 101 of the FX driver 406 is always turned on, and the wafer burn-in potential VBI is simultaneously supplied to all the sub word lines SWL0 to SWLn via the bonding pad BP1. By using the switch 101, the leakage current of the CMOS inverter constituting the main word line driver 401 and the FX driver 406 can be reduced.
[0019]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0020]
For example, in this embodiment, the main word line driver 401 is configured using a CMOS inverter, but can be configured using an N-channel MOS transistor.
[0021]
In the above description, the case where the invention made mainly by the present inventor is applied to a DRAM which is a field of use as a background of the invention has been shown. However, the invention can also be applied to an EPROM or an EEPROM. The present invention can also be applied to a word shunt type semiconductor memory device.
[0022]
The present invention can be applied to a semiconductor memory device including a word line driver in which at least a CMOS inverter supplies a selection potential to a word line.
[0023]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0024]
In other words, the switch provided in the path for supplying the operation power to the word line driver becomes a low leakage circuit that suppresses an undesired leakage current of the CMOS circuit constituting the word line driver, and a wafer burn-in potential supply circuit. It also becomes. That is, since the low leak circuit and the wafer burn-in potential supply circuit which are conventionally provided individually can be combined into one, the circuit configuration can be simplified.
[Brief description of the drawings]
FIG. 1 is an example circuit diagram of a word line driver provided in a semiconductor memory device of the present invention.
FIG. 2 is a block diagram illustrating an example of a semiconductor memory device according to the present invention.
FIG. 3 is a time chart of a word line selection operation and a wafer burn-in operation in the word line driver of the present embodiment.
FIG. 4 is a block diagram showing an example of another semiconductor memory device of the present invention.
FIG. 5 is an example circuit diagram of a word line driver provided in another semiconductor memory circuit of the present invention.
[Explanation of symbols]
100 word line driver 101 switch 102 selection circuit 103 all word line selection circuit WLn word line Xn * decode signal φ1 * switch control signal

Claims (2)

In a semiconductor memory device having a memory cell array in which selection terminals of a plurality of memory cells arranged in a matrix are coupled to sub-word lines of a hierarchical word line system and data terminals are coupled to bit lines.
A first address decoder for decoding a first address signal to form a main word line decode signal;
A main word line driver for drive the main word lines on the basis of the main word line decode signal,
A second address decoder for decoding the second address signal to form a sub word line decode signal;
An FX driver comprising a CMOS circuit capable of outputting an operation power supply for driving the sub word line based on the sub word line decode signal;
A sub-word line driver consisting of CMOS circuits provided corresponding to the respective sub-word lines to drive the dynamic sub-word line based on an output of the main word line driver output and the FX driver,
A first switch element arranged on that power supply path put on SL FX driver,
A second switch element arranged to operate electrostatic Minamotokei path definitive on texture in the word line driver,
In the first mode, the first switch element and the second switch element are controlled to be turned on in synchronization with the enable state of the row address strobe signal. In the second mode, the row address strobe signal is controlled regardless of the state of the row address strobe signal. A control circuit for controlling the first switch element and the second switch element to an ON state ;
The semiconductor memory device characterized by comprising a. 2. The semiconductor memory device according to claim 1, wherein the first mode is a memory access mode, and the second mode is a wafer burn-in mode .

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